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Jack of All Scales: A Versatile FPGA Tensor Block for MXFP Precisions
Published 15 Jul 2026 in cs.AR | (2607.13898v1)
Abstract: Modern deep learning workloads increasingly rely on narrow numerical formats to improve efficiency and reduce memory footprint. The recently standardized microscaling floating-point (MXFP) family of formats, including MXFP8, MXFP6, and MXFP4, offers a practical approach to low-precision inference, yet the digital signal processing (DSP) blocks in current FPGA architectures offer limited native support for these formats. In this work, we first present a comprehensive characterization of MXFP dot product implementations on Altera Agilex-5 FPGAs, exploring a range of strategies spanning pure soft logic, DSP blocks in fixed-point, floating-point, and tensor modes. Our results show that while the tensor mode delivers the highest arithmetic density for MXFP4 (E2M1) and MXFP6 (E2M3), it cannot implement MXFP6 (E3M2) or any MXFP8 precisions, forcing designers to fall back to lower-density alternatives. Motivated by this gap, we propose targeted modifications to the DSP block's internal tensor-mode architecture that enable native support for all MXFP precisions while retaining backward compatibility. We estimate the area cost of these modifications using a simplified version of the Agilex-5 DSP block core implemented using the open-source ASAP7 PDK. We evaluate a variety of modified DSP block designs that present a tradeoff between format coverage, arithmetic density, and area overhead. Our preferred design point increases the DSP tile area by 36%, corresponding to only 1.8\% of the total FPGA die area. We evaluate the device-level impact of our enhanced DSP block by comparing systolic array matrix multiplier implementations across all MXFP precisions, contrasting the best-available strategies on the existing architecture against designs leveraging our modified DSP block. Our results demonstrate an average throughput improvement of 4.2x across all supported MXFP formats.
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What this paper is about
This paper looks at how to make AI math run faster and more efficiently on FPGAs, which are chips you can “rewire” after they’re built. The authors focus on special, very small number formats called MXFP (microscaling floating point) that use fewer bits than normal, saving memory and energy while keeping good accuracy for AI tasks. They show:
- Today’s FPGA “calculator blocks” (called DSP blocks) don’t fully support all MXFP formats in their fastest mode.
- With a few smart changes inside these blocks, FPGAs could run all MXFP types much faster, with only a tiny increase in chip area.
The main questions the paper asks
In simple terms, the researchers wanted to know:
- How well do current FPGAs handle different tiny-number formats (MXFP4, MXFP6, MXFP8) used in AI?
- Which ways of building the math units on an FPGA are best for each format (using only general logic, using the built-in DSP calculators in different modes, or using the DSP “tensor” mode)?
- Can we tweak the DSP block’s fastest mode so it supports every MXFP format without giving up speed?
- If we make those tweaks, how much extra chip area does it cost, and how much speed do we gain?
How they approached it (explained simply)
Think of an FPGA as a giant board of electronic LEGO:
- Soft logic (LUTs/ALMs): lots of small, flexible LEGO pieces you can build anything with, but it might take many pieces.
- DSP blocks: built‑in, hardwired “calculator” bricks that are much faster and denser for math, but less flexible.
- Tensor mode: a special “high-throughput” setting in the DSP blocks designed to do many small dot-products (a key AI math operation) very quickly.
The team did three kinds of work:
- Measure and compare different build styles
They built the same core operation—32‑element dot products—in four ways across all MXFP types:
- Only soft logic (flexible but larger)
- “Packed” fixed-point multipliers inside DSPs (squeeze several small multiplications into one bigger multiplier—like fitting several tiny LEGO builds into one bigger shell)
- Native fp16 vector mode in DSPs (convert small numbers to half-precision floats and use the DSP’s float units)
- Tensor mode (the fastest DSP mode, if it fits)
They recorded how many resources each design used, how fast it ran, and how many such units could fit on a real device (an Altera/Intel Agilex-5 FPGA).
- Propose new DSP designs
They noticed the fastest mode (tensor mode) didn’t support some MXFP formats (especially MXFP8 and one MXFP6 variant), because its internal lanes were only 8 bits wide. They designed several small, targeted changes to the DSP’s tensor datapath so it could:
- Work directly on MXFP numbers (no big conversions outside)
- Handle all MXFP formats (MXFP4, both MXFP6 types, and MXFP8)
- Keep backward compatibility as much as possible
To check the cost, they built a simplified model of the DSP block and estimated its silicon area using a standard 7 nm chip “blueprint” (ASAP7) and chip design tools. They also carefully sized the connection circuits that tie the block into the FPGA’s routing (so the pin count wouldn’t blow up).
- Test the system-level impact They built “systolic arrays,” which are grids of tiny math units that pass values along like students handing papers across rows—perfect for matrix multiplication in AI. They compared arrays built on today’s DSPs vs. arrays using their modified DSP ideas to see overall speedups.
Key ideas explained with quick analogies
- Floating point with “shared scale” (MXFP): Like scientific notation where you write 3.14 × 102, but now a whole group of numbers shares the same “×10X”. This saves bits per number but keeps a big overall range.
- Dot product: Multiply and add pairs of numbers in two lists (like matching test scores and weights), then sum them up.
- Packed multipliers: If you have a big calculator that multiplies 18-bit numbers, and you only need 3- or 4-bit numbers, you can line up several small numbers inside the big input so the one big multiply secretly does several small multiplies at once.
- Systolic array: A checkerboard of tiny calculators passing data to neighbors every step, perfect for streaming matrix math.
What they found and why it matters
- On today’s FPGAs (Agilex-5), the best method depends on the MXFP format:
- For MXFP8 (E4M3, E5M2) and MXFP6 (E3M2): “Packed DSP” multipliers were best among current options, but still needed a lot of soft logic around them.
- For MXFP6 (E2M3) and MXFP4 (E2M1): Tensor mode (fastest) worked and delivered very high throughput.
- The fp16 vector mode worked for all formats but didn’t scale up in speed for smaller bit-widths.
Bottom line: current tensor mode is super fast but only for some MXFP types. It can’t handle MXFP8 or MXFP6 (E3M2), which forces designers to fall back to slower or less dense options.
- With their DSP changes, all MXFP formats can run in a fast, tensor-like way
They explored multiple design options and picked a favorite that:
- Adds about 36% area to each DSP tile (the DSP block plus its routing interfaces)
- Translates to only about 1.8% more total FPGA chip area (since DSPs are a small part of the chip)
- Keeps similar clock speed (around the same ~458–490 MHz range)
- Increases “lanes” (how many dot elements per block) for formats that already worked, and adds support for the previously unsupported ones
- Big speedups for AI math (dot products and matrices)
When they rebuilt 32‑element dot products with the new DSP:
- MXFP8 E5M2: from about 2.1 TFLOPS to about 12.4 TFLOPS (≈6×)
- MXFP8 E4M3: up to about 12.4 TFLOPS
- MXFP6 E3M2: up to about 16.5 TFLOPS
- MXFP6 E2M3: from 12.4 to about 16.5 TFLOPS
- MXFP4 E2M1: up to about 24.8 TFLOPS
On average, across formats, they report about a 4.2× throughput improvement for matrix multiplications using systolic arrays.
Why this matters: More speed per area means faster AI inference, lower cost, and lower energy for the same work—especially useful for data centers or edge devices that want to run modern AI models efficiently.
What this could change
- FPGA vendors could adopt these small DSP tweaks to offer native, high-speed support for the full MXFP family. That would:
- Keep FPGAs flexible as AI number formats evolve
- Make FPGAs more competitive with GPUs/ASICs for low-precision AI inference
- Reduce power and chip area needed to reach high throughput
- For developers, it simplifies building fast AI accelerators on FPGAs, because the fastest mode would “just work” for the most popular tiny formats (including MXFP8).
- The authors open-sourced their designs and benchmarks, so others can build on this work more easily.
Quick recap
- Problem: Fast DSP “tensor mode” on today’s FPGAs doesn’t support all the newest tiny-number formats (MXFP8, some MXFP6), limiting speed for those cases.
- Approach: Measure current options, then propose small, targeted DSP block changes to enable native MXFP in tensor-style hardware.
- Result: About 1.8% chip area increase yields big gains—around 4.2× average speedup across formats—with support for all MXFP types.
- Impact: Faster, more efficient AI inference on FPGAs with minimal hardware cost.
Practical Applications
Overview
Based on the paper’s characterization of MXFP implementations on Agilex-5 FPGAs, its mapping strategies (packed fixed-point, fp16 vector chaining, and tensor mode), and its proposed DSP tensor-mode enhancements (native MXFP support with a 36% DSP tile area increase ~1.8% of die area and average 4.2× throughput gains across MXFP formats), the following practical applications emerge. Each item notes target sectors, potential tools/products/workflows, and critical assumptions or dependencies.
Immediate Applications
These can be deployed on current Agilex-5 and similar FPGAs using the paper’s best-available mapping strategies and open-source designs.
- MXFP-optimized FPGA inference accelerators for deep learning
- Sector: Software/AI, Data Center, Edge/Robotics, Healthcare, Finance
- What: Build GEMM/systolic-array kernels for MXFP4/6/8 using the paper’s per-format mappings:
- E2M1/E2M3 via tensor mode
- E3M2/E4M3/E5M2 via packed fixed-point multipliers or fp16 vector chaining
- Tools/Products/Workflows:
- Use the paper’s open-source Verilog IP for MXFP dot products and systolic arrays (repo link in paper)
- Integrate with HLS (Vitis HLS, Intel HLS), RTL compilers, and DL compilers (TVM, XLA) via custom schedules/kernels for MXFP GEMMs and attention blocks
- Incorporate FloPoCo-based fp32 conversion and shared-scale handling in the dataflow
- Assumptions/Dependencies:
- MXFP quantization/calibration workflows (e.g., PTQ/QAT) for target models maintain accuracy; model/tooling support for block scaling (k=32) and shared scales
- Memory bandwidth is sufficient to realize compute gains; the optimistic peak TFLOPS assumes minimal frequency degradation at scale
- Faster, lower-cost LLM and transformer inference on FPGA clouds
- Sector: Cloud AI (e.g., AWS F1-like platforms), Enterprise AI
- What: Deploy MXFP6/8-compatible serving stacks for encoder/decoder blocks using the mapped kernels; reduce latency/cost for throughput-sensitive inference
- Tools/Products/Workflows:
- MXFP-aware runtime libraries (e.g., custom BLAS-like kernels), FPGA bitstreams with MXFP systolic cores, Kubernetes operators that schedule MXFP workloads
- Assumptions/Dependencies:
- Serving frameworks (vLLM, TensorRT-LLM pipelines adapted to FPGA) can export MXFP models; integration with tokenizer/IO pipelines hides block-scaling details
- Edge AI accelerators with improved perf/W and smaller footprint
- Sector: Embedded/Edge, Robotics, IoT, Industrial
- What: Use MXFP4/6 mappings (notably E2M1/E2M3 in tensor mode) to fit more compute per device at lower power for tasks like detection, SLAM, and speech
- Tools/Products/Workflows:
- Prebuilt MXFP kernels embedded in FPGA SoMs; firmware update paths for deploying MXFP bitstreams; on-device calibration to MXFP formats
- Assumptions/Dependencies:
- Thermal budgets and power delivery support higher arithmetic density; sensor/model pipelines remain accurate under MXFP quantization
- MXFP-aware FPGA IP cores and libraries
- Sector: IP Vendors, EDA, FPGA OEMs
- What: Package the paper’s best approaches as licensable IP (dot-product engines, systolic arrays) and library primitives (MXFP GEMM, convolution)
- Tools/Products/Workflows:
- RTL/HLS IP, parameterizable blocks for E2M1/E2M3/E3M2/E4M3/E5M2; automated multiplier-packing scripts; reference designs for Agilex-5
- Assumptions/Dependencies:
- Stable MXFP spec; CAD tool support for DSP mode selection and chaining; adequate verification suites for MXFP correctness (scale handling, corner cases)
- Compiler and toolchain enhancements for MXFP targeting
- Sector: EDA, ML Compiler Ecosystem
- What: Add passes that detect MXFP ops and choose the best mapping (tensor vs packed vs fp16 vector), schedule dataflows to exploit DSP cascades and side feeds
- Tools/Products/Workflows:
- TVM schedules, MLIR/XLA lowering patterns for MXFP dot/kernels; packer/unpacker codegen for shared scales; resource-aware placement templates
- Assumptions/Dependencies:
- Accurate cost models for ALM/DSP tradeoffs and frequency scaling; smooth integration with existing framework quantizers
- Academic teaching and benchmarking kits for low-precision arithmetic on FPGAs
- Sector: Academia
- What: Course labs and research prototypes using the open-source implementations to study MXFP vs int8/bf16 tradeoffs, systolic architectures, and DSP packing
- Tools/Products/Workflows:
- Ready-to-run projects (Quartus, simulation testbenches), reproducible scripts, datasets for accuracy vs throughput evaluations
- Assumptions/Dependencies:
- Access to Agilex-5 or similar boards; student familiarity with MXFP quantization and FPGA toolchains
- Energy efficiency and sustainability reporting for FPGA inference
- Sector: Policy, Data Center Operations
- What: Use MXFP-based accelerators to improve perf/W and include these metrics in ESG reporting and procurement evaluations
- Tools/Products/Workflows:
- Measurement frameworks correlating MXFP precision to energy per token/image/frame; standardized benchmarking suites
- Assumptions/Dependencies:
- MXFP pipeline maturity and repeatable measurement methodology across models and loads
Long-Term Applications
These require vendor silicon changes, broader ecosystem support, or additional research and scaling.
- Next-generation FPGA DSP blocks with native MXFP tensor modes
- Sector: Semiconductor, FPGA Vendors
- What: Incorporate the paper’s proposed DSP architecture (native MXFP inputs, expanded CSA, dot-8 baseline) into future FPGAs
- Benefits:
- ~36% DSP tile area increase (~1.8% die) for average 4.2× MXFP throughput gains; support for E2M1/E2M3/E3M2 and (optionally) E4M3/E5M2
- Tools/Products/Workflows:
- Full custom DSP design, verification, and PDK sign-off; updated CAD support for new modes; backward-compatible mode muxing
- Assumptions/Dependencies:
- Product planning alignment, area/power budgets, validation of NaN/Inf handling policies (paper drops some special encodings in certain iterations), and market demand for MXFP
- Standardized MXFP compilers and runtime stacks
- Sector: Software/AI Frameworks, EDA
- What: End-to-end MXFP support in mainstream frameworks (PyTorch, TensorFlow), compilers (TVM, XLA, OpenVINO), and runtime libraries targeting FPGA DSP tensor modes
- Tools/Products/Workflows:
- First-class abstractions for block scaling (k=32), shared-scale computation, calibration pipelines, and op fusion under MXFP
- Assumptions/Dependencies:
- Widespread adoption of MXFP in model zoos; robust PTQ/QAT recipes preserving accuracy at 4–8 bits; interoperability across CPU/GPU/FPGA backends
- MXFP-aware accelerator cards and appliances
- Sector: Hardware OEMs, Cloud Providers
- What: FPGA cards/edge boxes optimized around MXFP throughput (memory, interconnect, thermal) and shipped with MXFP-optimized bitstreams and SDKs
- Tools/Products/Workflows:
- PCIe/CCIX/CXL-enabled solutions with shared-scale-friendly DMA pipelines; deployment SDKs for LLMs/CV/ASR in MXFP
- Assumptions/Dependencies:
- Customer acceptance of MXFP accuracy; integration with enterprise MLOps; serviceability and long-term maintenance of MXFP pipelines
- Cross-standard low-precision support (MXFP, NVFP4, MSFP) in reconfigurable DSPs
- Sector: Semiconductor, IP Vendors
- What: Generalize the proposed DSP enhancements to support multiple block-scaled formats (e.g., Nvidia NVFP4, MSFP) via configurable scale-handling and lane widths
- Tools/Products/Workflows:
- Reconfigurable multiplier fabrics with programmable alignment/CSA trees; format-agnostic input adapters
- Assumptions/Dependencies:
- Coordination with standard bodies; area/power costs remain acceptable; CAD flow support for mode reconfiguration
- ASICs and chiplets inspired by MXFP-native tensor cores
- Sector: Semiconductor (Accelerators), Hyperscalers
- What: Apply the paper’s architectural lessons (narrow FP multipliers, alignment + CSA strategies, native format paths) to ASIC tensor cores or chiplets
- Tools/Products/Workflows:
- Co-design of block-scaled formats and compute units; die-to-die links carrying block scales; compiler/runtime co-optimization
- Assumptions/Dependencies:
- Workload stability around block-scaled FP; validation of accuracy and resilience; cost and NRE justifications
- Safety-critical and regulated-domain deployment (healthcare, automotive)
- Sector: Healthcare, Automotive, Aerospace
- What: Certify MXFP-based FPGA inference where reduced precision is acceptable with provable accuracy bounds and robust failover paths
- Tools/Products/Workflows:
- Formal verification of MXFP arithmetic; conformance tests for scale handling; mixed-precision fallback strategies
- Assumptions/Dependencies:
- Regulatory acceptance of low-precision inference; availability of datasets/protocols to validate MXFP safety and robustness
- Policy and procurement guidelines for interoperable low-precision AI
- Sector: Policy, Standards Bodies, Public Sector IT
- What: Encourage adoption of open MXFP standards in public procurements to reduce vendor lock-in and improve energy efficiency
- Tools/Products/Workflows:
- Benchmarks and RFP checklists that recognize MXFP performance/efficiency; validation suites for MXFP compliance
- Assumptions/Dependencies:
- Continued industry support for OCP MX specification; clear measurement standards and comparability across vendors
- Automated design-space exploration (DSE) for MXFP mappings
- Sector: EDA, Academia
- What: DSE tools that pick the optimal mapping (tensor vs packed vs fp16 vector) per layer/model and co-optimize clocking, placement, and routing
- Tools/Products/Workflows:
- Cost models integrating ALM/DSP utilization, routing congestion, and frequency scaling; layer-wise and end-to-end throughput/latency optimizers
- Assumptions/Dependencies:
- Accurate prediction of frequency degradation at high utilization; calibration of models across FPGA families and tool versions
- Broadening MXFP beyond k=32 and into training or mixed-precision regimes
- Sector: Research, AI Infrastructure
- What: Explore other block sizes and training-time use with error-compensation; mixed-precision accumulations with fp32/bf16 for stability
- Tools/Products/Workflows:
- New quantization/training recipes; hardware support for alternative k and accumulation mixes; evaluation suites for convergence/accuracy
- Assumptions/Dependencies:
- Training stability under block scaling; memory/computation tradeoffs remain favorable for alternative k values
In summary, the paper’s characterization immediately enables better MXFP deployments on today’s FPGAs, while its DSP architecture proposals chart a feasible path—at low die-area cost—toward native MXFP tensor modes that can materially raise future FPGA performance and efficiency for low-precision AI workloads.
Glossary
- Arithmetic density: Number of operations achievable per unit area or resource in hardware; higher density means more compute packed into the same silicon. "the tensor mode delivers the highest arithmetic density for MXFP4 (E2M1) and MXFP6 (E2M3)"
- ASAP7 PDK: An academic 7 nm process design kit used for ASIC-style implementation and area estimation. "using the open-source ASAP7 PDK."
- Barrel shifters: Hardware shifters that can shift data by a variable amount in a single cycle, often used for alignment. "align them using barrel shifters controlled by the sum of per-element exponents."
- bfloat16: A 16-bit floating-point format (Brain floating-point) with 8-bit exponent and 7-bit mantissa used in ML hardware. "achieve 2.8-16.4× higher multiply-accumulate density per unit area compared to 16-bit Brain floating-point (bfloat16)"
- Block floating-point (bfp16): A numeric format where a block of numbers shares an exponent with individual mantissas, here 16-bit. "used a 16-bit block floating-point (bfp16) representation"
- Block-scaled floating-point: Floating-point formats where elements share a scale/exponent per block to reduce per-element bits. "defines a family of block-scaled floating-point formats"
- Carry-save adder (CSA) tree: A tree of adders that accumulates many operands efficiently by delaying carries, used in multiply-accumulate pipelines. "reduced using a carry-save adder (CSA) tree"
- COFFE: A tool for optimizing FPGA routing and interface circuits via transistor sizing. "optimized using COFFE~\cite{COFFE2_2019}"
- Connection block: FPGA routing component that connects logic block pins to routing tracks. "switch block and connection block"
- Dedicated accumulator chains: Hardwired connections between adjacent DSPs or tiles for fast accumulation across blocks. "64 dedicated accumulator chains between DSP blocks in the same column."
- Dot-10: A tensor-mode configuration that computes dot products over 10 lanes per unit. "implementing two dot-10 operations ( and )"
- DSP48E2: A Xilinx DSP hard block primitive with fixed and flexible precision features. "modifications to the Xilinx DSP48E2 block"
- EM notation: A shorthand for floating-point formats indicating e exponent bits and m mantissa bits. "we use the notation EM to denote a floating-point format with exponent bits and mantissa bits (e.g., E4M3 denotes 4 exponent bits and 3 mantissa bits in addition to a sign bit)"
- FloPoCo: A generator/toolbox for floating-point and fixed-point hardware operators. "generated using FloPoCo~\cite{de2011flopoco}"
- HAMMER flow: An open-source ASIC design flow that orchestrates synthesis and place-and-route tools. "We run the ASIC implementation tools through the HAMMER flow~\cite{liew2022hammer}"
- Kulisch-style wide fixed-point accumulator: An exact accumulation method that uses a very wide fixed-point register to avoid rounding during summation. "comparing exact accumulation (using a Kulisch-style wide fixed-point accumulator)"
- Local crossbar: A small routing crossbar near a hard block (e.g., DSP) for selecting and steering local inputs. "a local crossbar for DSP block inputs"
- Microscaling floating-point (MXFP): A family of block-scaled floating-point formats (MXFP8/6/4) standardized for efficient low-precision ML inference. "microscaling floating-point (MXFP) family of formats"
- Microsoft floating-point (MSFP): A block-shared-exponent floating-point scheme used in Microsoft Brainwave NPUs. "used Microsoft floating-point (MSFP) formats."
- NVFP4: Nvidia’s micro FP format that uses a shared fp8 E4M3 scale per block of fp4 elements plus an additional tensor-level scale. "Nvidia's NVFP4 uses an fp8 E4M3 shared scale for a block of sixteen fp4 numbers and applies another fp32 scale per tensor"
- Open Compute Project (OCP): An industry consortium that, among other efforts, standardizes hardware specifications like MX formats. "defined the Microscaling (MX) specification under the Open Compute Project (OCP)"
- Ping-pong register cascades: Alternating on-chip register banks that allow overlapping compute with data loading for high throughput. "pre-loaded internal ping-pong register cascades."
- Place and route (PnR): The ASIC/FPGA backend process of placing components and routing interconnections to meet timing/area. "for place and route (PnR)."
- Side feed mechanism: A data loading path that streams elements into on-chip cascades without stalling compute. "the side feed mechanism loads two elements at a time to one cascade over 10 cycles"
- Significand: The fractional part of a floating-point number (mantissa plus implicit leading 1 in normal numbers). "multiplying the narrow significands (i.e., mantissa + implicit one)"
- Standard cell: Pre-designed logic gate cells used to build ASIC blocks like modified DSP cores. "We implement the DSP block core in standard cell using the ASAP 7nm process design kit (PDK)"
- Switch block: FPGA routing component that switches signals between intersecting routing tracks. "switch block and connection block"
- Systolic array: A regular array of processing elements that pass data rhythmically for high-throughput matrix operations. "systolic array matrix multiplier implementations"
- Tensor cores: Specialized matrix-multiply units in GPUs optimized for low-precision tensor operations. "supports fp4 and fp6 operations in its fifth-generation tensor cores~\cite{blackwell2024}"
- Tensor mode: A DSP block operating mode optimized for vector dot products with shared operands and internal accumulation. "The tensor mode, illustrated in Fig.~\ref{fig:baseline_aitb}, provides the highest arithmetic density."
- TFLOPS: Trillions of floating-point operations per second, a throughput metric for compute accelerators. "achieved up to 35.9 tera floating-point operations per second (TFLOPS)"
- Two's complement: A number representation for signed integers enabling straightforward addition/subtraction in hardware. "converted to two's complement representation"
- Vector chaining: A technique that chains multiple DSPs to accumulate partial products into longer dot products efficiently. "we adopt the vector chaining technique of Langhammer and Pasca"