FAPlace: Joint Optimization of Chiplet Placement and Interposer Footprint for 2.5D Systems

Abstract: The placement of chiplets on a silicon interposer is a pivotal step in 2.5D system integration, yet existing placement approaches typically assume a pre-defined interposer footprint. This creates a circular dependency: the optimal footprint cannot be known without first solving the placement, while the placement itself is constrained by the given dimensions. An undersized interposer may exclude feasible placements, while an oversized one yields unnecessarily sparse solutions. Moreover, even when the footprint area is minimized, few existing approaches explicitly control the interposer's aspect ratio. To jointly address these challenges, we propose FAPlace, a footprint aware mask guided sequential placement framework. FAPlace operates on a sufficiently large canvas, eliminating the circular dependency by allowing the optimal interposer footprint to emerge as an output of the optimization rather than a pre-specified input. At its core is a novel footprint mask that fuses area compactness with an aspect ratio penalty into a unified spatial cost map. Integrated with wirelength and thermal guidance masks, FAPlace delivers holistic multi-physics optimization in a deterministic, single pass process. Experimental results demonstrate that FAPlace reduces wirelength and footprint area while achieving near-unity aspect ratios, without compromising on thermal performance.

• The paper introduces FAPlace, a deterministic mask-guided framework that jointly places chiplets and discovers a compact interposer footprint while optimizing wirelength, temperature, area, and aspect ratio.
• Experiments on five benchmarks with up to 36 chiplets show about 2× lower wirelength, comparable peak temperature, near-square footprints, and roughly 4× faster runtime than TAP-2.5D.
• The footprint mask and adaptive thermal-spacing method produce thermally safe, compact layouts without a pre-defined canvas, but larger benchmarks, automatic hyperparameter selection, and routing or warpage constraints remain open challenges.

FAPlace is a mask-guided sequential placement framework for 2.5D chiplet integration that removes the requirement for a pre-defined interposer footprint, treating the footprint as an output of the optimization rather than an input (2607.02610). The work addresses two coupled deficiencies in prior chiplet placement methodologies: the circular dependency between placement quality and canvas specification, and the absence of any explicit control over interposer aspect ratio (AR).

Motivation and problem formulation

Existing approaches to chiplet placement—simulated annealing (TAP-2.5D, STAMP-2.5D), sequence-pair methods, analytical formulations (ATPlace2.5D, TACPlace), and reinforcement learning—all require a pre-specified interposer size. This creates a circular dependency: an undersized interposer excludes feasible placements, while an oversized one produces sparse layouts with extreme aspect ratios. In practice, designers resort to manual trial-and-error over canvas sizes. Additionally, although industry-standard 2.5D packages almost universally adopt near-square interposer form factors, and elongated geometries may exacerbate CTE-mismatch-induced warpage along the longer axis, no prior work incorporates AR as an explicit objective.

The problem takes as input a set of chiplets with dimensions and TDPs, a netlist, and pin clumps, and determines coordinates and orientations ($0^\circ$ or $90^\circ$) minimizing three objectives: total wirelength via a flow-based multi-commodity formulation, peak steady-state temperature $T_p$, and a composite footprint objective combining bounding box area $A = W_{bb} \times H_{bb}$ with deviation from a target aspect ratio $AR_{\text{tgt}}$.

Framework

FAPlace places chiplets sequentially on a deliberately oversized canvas, so feasibility issues vanish and the final footprint emerges from the optimization itself. Five components constitute the framework:

• Connectivity-driven ordering: the largest chiplet seeds the placement; each subsequent chiplet maximizes total connection weight to the already-placed set.
• Footprint mask: the central contribution. For each candidate grid cell, it computes a normalized area-expansion cost—the increase in bounding box area relative to the incoming chiplet's area—and a quadratic AR penalty $$\left(\max(W_{\text{new}}/H_{\text{new}}, H_{\text{new}}/W_{\text{new}}) - AR_{\text{tgt}}\right)^2$$, fused with weight $\eta$. The quadratic form penalizes mild deviations lightly but extreme elongation severely.
• Wire and thermal masks: Manhattan-distance-based wirelength approximation to placed neighbors, and HotSpot-derived temperature maps applied only when placing high-power chiplets above a threshold.
• Unified mask synthesis: normalized masks are combined into a single cost map; a position mask filters overlaps, and greedy selection picks the optimal location and orientation among $2G^2$ candidates per step. The procedure is deterministic and completes in exactly $N$ steps.
• Adaptive thermal-spacing (ATS): after footprint extraction onto a tight bounding box, binary search finds the minimum thermal weight $\beta^*$ satisfying a peak temperature limit $90^\circ$0, yielding the tightest thermally safe packing.

Experimental results

Evaluation covers five benchmarks (6–36 chiplets), including two real-world architectures (MultiGPU, CPU-DRAM), against TAP-2.5D. Notably, TAP-2.5D is given FAPlace's own output interposer side length as its input canvas—a favorable setting for the baseline—and FAPlace still dominates:

Metric	TAP-2.5D	FAPlace
Runtime (avg.)	3.99×	1×
Peak temp (avg.)	1.02×	1×
Wirelength (avg.)	1.99×	1×

FAPlace reduces wirelength by approximately 2× on average (e.g., Sys 3: 276 m → 79 m; Sys 5: 43 m → 19 m), matches thermal performance within 1.02× on average, and runs roughly 4× faster due to its deterministic single-pass procedure versus stochastic annealing.

When both methods run on the same sufficiently large canvas (Sys 1 case study), TAP-2.5D degrades sharply—wirelength of 339 m versus 95 m, bounding box area of 106 cm² versus 29 cm², and AR of 1.40 versus 1.12 at comparable peak temperature—demonstrating that SA-based placement depends heavily on a well-specified footprint to produce compact results.

Ablation confirms the footprint mask's role: removing it leaves wirelength and temperature essentially unchanged (0.99×–1.00×) but increases average AR by 1.80× and required interposer side length by 1.40×. Two cases illustrate why both components matter: on Sys 1, dropping the mask yields smaller raw area but AR surges from 1.12 to 3.07, forcing an 85 mm interposer instead of 56 mm; on Sys 2, AR stays acceptable but area nearly doubles from 15 to 28 cm². A sensitivity sweep over $90^\circ$1 shows that disabling the AR penalty entirely yields minimal area but an extreme AR near 4.5, while $90^\circ$2 converges AR to approximately 1.0. The ATS study on Sys 2 shows convergence in three epochs from a dense, thermally violating core to a dispersed U-shaped configuration meeting a 96 °C limit at minimal wirelength.

Limitations and open questions

The paper concedes several constraints on generality. Comparisons exclude all prior methods except TAP-2.5D because their implementations are not publicly available, so the reported advantages rest on a single baseline. The benchmark suite is small (at most 36 chiplets, average degree ≤ 2.43), leaving scalability to large-scale 2.5D designs untested. Hyperparameters ($90^\circ$3, $90^\circ$4 ranges) are set per design rather than derived automatically, and the sequential greedy ordering means placement quality may depend on the connectivity-driven order without any analysis of ordering sensitivity. Whether the quadratic AR penalty generalizes to non-square target form factors, and how the footprint mask interacts with routing congestion or mechanical/warpage constraints beyond the AR proxy, remain open questions.

Conclusion

FAPlace reformulates 2.5D chiplet placement so that the interposer footprint is discovered rather than assumed, through a unified spatial cost map fusing area compactness and aspect ratio compliance with wirelength and thermal guidance. On benchmarks up to 36 chiplets, it achieves roughly 2× lower wirelength, near-unity aspect ratios, matched thermal performance, and ~4× faster runtime than a thermally aware SA baseline that is granted a favorable pre-specified canvas.