FlowPlace: Flow Matching for Chip Placement

Abstract: Chip placement plays an important role in physical design. While generative models like diffusion models offer promising learning-based solutions, current methods have the following limitations: they use random synthetic data for pre-training, require long sampling times, and often result in overlaps due to their dependence on gradient-based solvers during the sampling process. To overcome these issues, we propose FlowPlace, which features mask-guided synthetic data generation, flow-based efficient training with flexible prior injection, and hard constraint sampling for overlap-free layouts. Experiments on OpenROAD and ICCAD 2015 benchmarks show FlowPlace achieves better PPA metrics, 10-50$\times$ faster sampling efficiency, and zero overlaps.

• The paper introduces a novel flow matching framework using deterministic ODE trajectories to generate legally compliant and efficient macro placements.
• It employs a mask-guided synthetic data generator and a hard constraint guided sampling mechanism to ensure zero overlaps and improved PPA metrics.
• Experimental results demonstrate significant runtime acceleration and consistent performance gains over RL and diffusion-based methods on standard benchmarks.

FlowPlace: Flow Matching for Chip Placement

Overview

The paper "FlowPlace: Flow Matching for Chip Placement" (2604.23658) presents a novel generative framework for macro placement in VLSI physical design, leveraging flow-based generative models equipped with domain-specific priors and hard constraint satisfaction. The core contributions are a mask-guided, domain-aware synthetic dataset generator, a flow-matching architecture for efficient and flexible training/inference, and a hard constraint guided sampling mechanism ensuring strictly legal (non-overlapping) placements. The experimental results on OpenROAD and ICCAD 2015 benchmarks demonstrate consistent improvement in power, performance, and area (PPA) metrics, 10–50$\times$ acceleration of sampling, and strict overlap avoidance compared to both reinforcement learning (RL) and diffusion-based competitors.

Figure 1: Comparison of placement performance on superblue7. EfficientPlace (RL-based) places macros sequentially, while ChipDiffusion and FlowPlace (generative model-based) simultaneously move all macro positions. FlowPlace demonstrates superior performance with the lowest HPWL and zero overlap.

Technical Contributions

Mask-Guided Synthetic Data Generation

The mask-guided generator addresses the lack of high-quality, large-scale annotated chip layouts for supervised learning. Unlike prior random-sampling schemes, mask-guided sampling iteratively selects macro positions based on a boundary proximity heuristic—favoring placing larger macros near the boundary, a practice widely adopted by expert designers for routability and congestion mitigation. This strategy is implemented efficiently on GPU by grid-discretizing the canvas and assigning scores to each candidate cell based on its squared inverse distance to the chip boundary.

The result is synthetic training data whose spatial distribution, macro clustering, and legal positioning closely resemble real designs. Ablations confirm that this synthetic data—when used to train generative models—largely closes the synthetic-real domain gap and leads to superior downstream PPA outcomes.

Flow Matching Paradigm

Differentiating from diffusion-based models, FlowPlace leverages the flow matching framework, learning a deterministic trajectory (ODE) that maps a flexible source distribution (preferably a uniform distribution over the legal canvas) to the data-generating distribution defined by the mask-guided placements. The velocity field is parameterized by a neural network combining GATv2 and global attention layers, consuming both spatial (macro coordinates) and topological (graph connectivity, pin offsets) information.

Training minimizes the conditional flow matching loss, regressing network outputs directly onto the analytically known velocity $(x_1-x_0)$ from source to target placements. Unlike stochastic, noise-scheduled sampling of denoising diffusion models, this approach achieves high-fidelity, legal placements with 20–50 integration steps, radically lowering inference time and eliminating sensitivity to hyperparameter choices in noise scheduling.

Figure 2: Progressive constraint enforcement process of hard constraint guided sampling. Only one macro is depicted for clarity.

Hard Constraint Guided Sampling

To guarantee physically legal, overlap-free macro placements, FlowPlace innovates beyond gradient-based guidance (which is common but neither sufficient nor efficient for strict constraint satisfaction). At each integration step, three operations are conducted:

1. Extrapolate: Use the learned ODE to predict the final positions,
2. Project: Apply a grid-based, parallelized legalization operator that greedily corrects macro positions to resolve overlaps, minimizing deviation from predicted positions,
3. Correct and Interpolate: Update the velocity field so future steps flow toward the feasible projection.

This mechanism enables progressive, smooth, and constraint-compliant macro migration trajectories that ensure legality throughout the generative process, as illustrated in Figure 2.

Comparative Assessment and Results

FlowPlace outperforms state-of-the-art baselines across all critical PPA metrics, including routed wirelength, congestion overflow, timing slack, power, and area, on both synthetic and real-world benchmarks. In direct comparison with RL-based sequential placers (EfficientPlace, MaskPlace), FlowPlace achieves both higher solution quality and multi-order-of-magnitude improvements in runtime, since it simultaneously determines all macro coordinates without requiring circuit-specific rollouts.

Figure 3: Placement layouts and congestion visualization on superblue1. Red points highlight congestion-critical regions.

Compared to ChipDiffusion (a denoising generative model), FlowPlace consistently achieves lower routed wirelength with strict zero-overlap and up to 50$\times$ faster inference. The hard constraint mechanism also ensures legality from the first to the last sampling step—unlike diffusion, which relies on external gradient-based corrections that may not eliminate all violations.

Figure 4: Relative average results of rWL, Overlap, and Runtime between ChipDiffusion and FlowPlace across ICCAD 2015 and OpenROAD benchmarks (values for ChipDiffusion normalized to 100\%).

Ablations substantiate the critical impact of both mask-guided data synthesis and uniform source priors in the flow-matching paradigm, yielding consistently improved macro placement and PPA metrics. Visualizations confirm improved congestion distribution and clustering regularity in resulting layouts, as highlighted in Figure 3.

Implications and Future Directions

FlowPlace demonstrates that incorporating VLSI domain knowledge at the data generation and modeling level, and leveraging deterministic flow-matching generative frameworks, leads to robust and scalable macro placement tools that seamlessly satisfy hard physical constraints. The methodology opens the door for more hierarchical, end-to-end, and multi-modal generative models targeting additional design stages or constraints, such as cell placement, timing closure, or power distribution. Its runtime efficiency enables integration into full EDA flows—potentially facilitating rapid design space exploration via zero-shot or hybrid optimization, and further enabling solution diversity crucial for design-for-manufacturing robustness.

The approach also highlights the advantages of flexible prior injection, constraint-aware trajectory design, and the separation of generative modeling and legalizer operations, suggesting that future AI-driven chip design methodologies could see broader adoption of flow matching and related generative paradigms.

Conclusion

FlowPlace establishes flow-matching generative modeling as a highly effective blueprint for legal and efficient VLSI macro placement, achieving superior PPA outcomes and sampling efficiency relative to both RL- and diffusion-based approaches. The combination of domain-aware synthetic data, efficient deterministic flow, and strict constraint enforcement creates a paradigm that generalizes robustly to new designs and is well-suited for integration in industrial EDA pipelines. This work forms a solid foundation for further innovation in generative modeling for EDA and strongly motivates future research incorporating hierarchical constraints and broader physical design objectives into generative frameworks.