CLIP-3D: Closed-Loop Evaluation of Performance and Physical Constraints for 3D ICs

Abstract: 3D integration packs more power into a smaller footprint, so a candidate design's actual throughput depends on its layout: which macro sits on which tier, where the hot spot lands, and how cache geometry maps to access cycles. Architectural simulators like gem5 report IPC under idealized timing. They do not produce the per-block power map, the cache cycle counts, or the 3D layout that decide the realized billion-instructions-per-second (BIPS), so early-stage 3D-IC exploration selects designs without accounting for the effects that decide whether they throttle on silicon. We present CLIP-3D, a shift-left flow that exposes 3D layout-driven thermal, wire, and cache effects to early-stage architectural exploration before any sign-off tool is invoked. The first stage lifts an architectural configuration into a physical block representation: McPAT for per-block dynamic and leakage power, CACTI for cache geometry and access cycles, and a HotSpot-compatible 3D stack discretization. The second stage runs an analytical 3D thermal-aware floorplanner over that representation. The floorplanner objective embeds a closed-form sustained-frequency expression derived from the linearity of HotSpot's steady-state operator and the standard CMOS power-frequency decomposition. Cross-tier macro assignment and in-plane placement are co-optimized for the realized BIPS rather than for a half-perimeter wirelength (HPWL)-plus-temperature surrogate with hand-tuned weights.

• The paper introduces a shift-left evaluation framework that integrates architectural simulation with physical layout effects to guide design selection.
• It employs a closed-form thermally-sustainable frequency expression and an analytical floorplanner to accurately capture performance throttling and interconnect penalties.
• Empirical results demonstrate up to a 24.77% improvement in realized BIPS and reveal significant ranking divergences against IPC-only estimates.

CLIP-3D: Closed-Loop Evaluation for Early-Stage 3D IC Design Selection

Motivation and Problem Formulation

The proliferation of 3D integration in IC design arises from the need to meet escalating computational demands within stringent footprint constraints. 3D stacking, whether monolithic or TSV-based, enables increased on-chip density but amplifies thermal and interconnect challenges. Traditional architectural simulators (e.g., gem5, SimpleScalar) operate under idealized timing conditions, neglecting layout-dependent thermal, wire, and cache latency effects that directly impact realized throughput (BIPS). Consequently, early architectural exploration frequently misguides design selection, ignoring critical layout-driven physical constraints that ultimately throttle silicon performance.

The central proposition of "CLIP-3D: Closed-Loop Evaluation of Performance and Physical Constraints for 3D ICs" (2607.12788) is a shift-left methodology that exposes these layout-driven effects—thermal throttling, interconnect penalties, and cache timing—to the architectural exploration phase, facilitating informed design selection before physical implementation or sign-off.

Architecture-to-Physical Lifting Pipeline

CLIP-3D advances by bridging architectural simulation and physical layout evaluation through a systematic lifting pipeline, integrating gem5, McPAT, CACTI, and HotSpot. Each candidate architecture (vector $a$, physical layout $p$) is decomposed into:

• Per-block Power and Area: Extracted via McPAT, delivering dynamic and leakage power for subsequent thermal modeling.
• Cache Access Cycles: CACTI-calibrated access times, translated to gem5 cycle counts, reflecting true cache geometry.
• 3D Stack Discretization: Layout rasterized to a uniform grid for thermal analysis, ensuring compatibility with HotSpot's 3D steady-state solver.

Latency penalties from vertical TSVs, inter-tier signaling, and shared-cache arbitration are parameterized into a discrete latency vector, fed back into gem5 for IPC calibration reflecting physical layout-induced delays. This separation of thermal and latency evaluation is a methodological advancement, simplifying pipeline orchestration and enabling scalable design space exploration.

Closed-Form Sustained Frequency Derivation

A notable contribution is the derivation of a closed-form expression for thermally-sustainable clock frequency, leveraging the linearity of HotSpot's steady-state solution and CMOS power-frequency scaling. For a candidate layout $d$, the sustainable frequency $f_{sus}$ is given by:

$$f_{sus}(d) = \max\left(f_{min}, \frac{f_0 \left[T_{safe} - T_{amb}\right] - \gamma}{(1-\gamma)\left[ T_{max}(d; f_0) - T_{amb} \right]} \right)$$

where $\gamma$ is the leakage fraction, $T_{max}$ is HotSpot-computed peak die temperature at nominal $f_0$, and $T_{safe}$ is the silicon reliability limit. This analytic form eliminates the need for iterative in-loop HotSpot solves, which are computationally expensive, and enables embedding physical constraints directly into layout optimization objectives.

Analytical 3D Thermal-Aware Floorplanner

CLIP-3D features an analytical floorplanner that co-optimizes macro tier assignment and in-plane placement for realized BIPS, eschewing surrogates like HPWL-plus-temperature weighted sums. The layout optimizer operates over:

• The closed-form sustained frequency, precisely capturing throttle effects;
• Discrete wire and TSV penalties, reflecting true interconnect costs;
• Cache and memory geometries, influencing both thermal and latency profiles.

Optimization is performed using L-BFGS-B, avoiding repeated thermal simulation by employing the analytic temperature proxy. Final candidate layouts are validated with a single HotSpot pass for consistency and accuracy.

Numerical Evaluation and Comparative Analysis

Empirical evaluation spans five workloads (FFT, CHOLESKY, STREAM, MATMUL, STENCIL) across 20 architectural configurations each, under two distinct cooling envelopes. The pipeline demonstrates:

• Ranking Divergence: Kendall-$\tau$ analysis reveals severe ranking mismatch between IPC-only and physically aware design selection, especially under stressed cooling where up to 100% of configurations experience thermal throttling. In multiple instances, IPC-optimized designs rank at or below average in realized BIPS, with Kendall-$p$0 as low as -0.36 and best-case gaps exceeding 1.12×.
• BIPS Gains: CLIP-3D achieves a mean realized BIPS improvement of 13.75% (up to 24.77%) on thermally-constrained designs versus deterministic shelf-pack baselines. Even on headroom configurations (non-throttled), wire-driven gains average 5.82%, with outliers at 79.02% stemming from optimal layout-driven L2 placement.
• Pareto Frontier Performance: Against canonical and surrogate-search floorplan baselines, CLIP-3D matches realized BIPS at 2.0–2.9× lower wall time per configuration, as the closed-form frequency expression obviates in-loop HotSpot calls.
• Conservative vs. Realized Estimates: IPC-only estimates are systematically conservative—layout-dependent latency penalties recovered via gem5 back-annotation drive an additional 8–10% realized BIPS uplift over paper formulas.

Practical and Theoretical Implications

The implications of CLIP-3D are both architectural and methodological. Designers can now evaluate candidate microarchitectures with full visibility into thermal, wire, and cache effects, ensuring selections maximize silicon-relevant throughput. Thermal-aware floorplanning is elevated from surrogate-based heuristics to analytic co-design, directly integrating architectural and physical optimization objectives.

Practically, this enables faster, more accurate early-stage design exploration, reducing the risk of costly post-layout surprises related to throttling or wire delays. The analyticity and modularity of the pipeline make it readily adaptable to emerging 3D IC paradigms, such as microfluidic cooling or advanced packaging.

Theoretically, the approach sets a precedent for shift-left evaluation in 3D IC CAD, advocating for integrated architecture-to-layout flows that capture cross-tier coupling effects. As cooling technologies evolve and workloads diversify, closed-loop frameworks like CLIP-3D will be integral to robust, scalable, and multi-objective IC co-design.

Conclusion

CLIP-3D presents a principled, analytically grounded methodology for exposing layout-driven constraints in early-stage 3D IC architectural exploration. By fusing architectural simulation, device-level modeling, and closed-form thermal analytics, CLIP-3D robustly optimizes for realized throughput under physical constraints, aligning design selection with what silicon actually delivers. The approach demonstrates strong numerical gains, computational efficiency, and methodological extensibility—paving the way for broader adoption of shift-left CAD flows in 3D IC design, where architecture and physical design must be co-optimized from the outset (2607.12788).