Programmable Probabilistic Computer with 1,000,000 p-bits

Abstract: Probabilistic computers built from p-bits have been proposed as hardware accelerators for sampling and optimizing Ising models, but existing systems have been confined to a single chip, capped by its capacity and memory bandwidth. Here we break this limit by networking FPGAs into a single Ising machine far larger than any one device could hold, realizing a programmable probabilistic computer with one million p-bits. The machine performs Gibbs sampling at over a trillion flips per second while keeping every coupling weight in local on-chip memory. During execution, devices exchange nothing but 1-bit boundary states. This architecture exposes a question fundamental to any distributed sampler: how frequently boundary information must be refreshed for a partitioned machine to behave as an unpartitioned one. Using three-dimensional Edwards-Anderson spin glasses, we show that the answer is set by a single timing ratio, eta = f_comm/f_p-bit, of the boundary-exchange frequency to the local p-bit update frequency. Above a topology-dependent threshold, the distributed machine matches a monolithic GPU reference. Below it, residual energy still decays as a power law but with a reduced exponent, turning parallelism into a quantifiable throughput-accuracy tradeoff. A theoretical cluster mean-field model reproduces the same behavior, showing that this tradeoff is a universal property of partitioned stochastic dynamics. These results provide a programmable million-p-bit platform, demonstrated across spin glasses, Max-Cut, and Boolean satisfiability, together with a quantitative design rule for scaling probabilistic computers beyond the single-chip limit.

• The paper introduces a distributed architecture that leverages 1,000,000 p-bits on multiple FPGAs to achieve high-throughput sampling and combinatorial optimization.
• It demonstrates that the solution quality depends solely on the communication-to-p-bit-update ratio, allowing a tunable tradeoff between speed and accuracy.
• Empirical benchmarks confirm significant performance gains, including up to 62× faster processing and state-of-the-art results on spin glass, Max-Cut, and 3SAT problems.

Programmable Probabilistic Computing with One Million p-bits: Architecture, Scaling, and Theoretical Principles

Introduction

The work "Programmable Probabilistic Computer with 1,000,000 p-bits" (2606.25313) demonstrates a distributed architecture for scalable stochastic computation by networking field-programmable gate arrays (FPGAs) into a programmable Ising machine with one million probabilistic bits (p-bits). This system represents a significant advance in hardware realizations of probabilistic computers targeting high-throughput sampling and combinatorial optimization tasks, pushing the limits of prior single-chip designs by orders of magnitude in both system size and Gibbs sampling throughput.

Architecture and Design Principles

The principal technical innovation is the construction of a distributed sparse Ising machine (DSIM) in which p-bits and their interactions are partitioned across multiple FPGAs. Each subgraph's coupling weights are stored locally, and the only run-time communication consists of exchanging 1-bit boundary states across device boundaries at controlled rates. The architecture ensures all local computation is performed at maximal on-chip bandwidth without incurring the off-chip memory wall that limits monolithic designs.

A critical architectural insight is the decoupling of processing (local p-bit flips) and communication (boundary state exchanges). The propagation of boundary information is managed independently of local p-bit update clocks, enabling both precise experimentation and the establishment of a single dimensionless ratio, $n = f_{\mathrm{comm}} / f_{\mathrm{p\text{-}bit}}$, as the governing parameter for distributed stochastic sampling. To mitigate the congestion and bandwidth penalties inherently present in physical non-all-to-all topologies, hardware-aware partitioning with a Potts cost function is introduced, emphasizing co-location of highly coupled nodes and minimizing long-range cut edges.

Timing Ratio as the Fundamental Scaling Law

The exhaustive empirical analysis reveals that the solution quality of the distributed Gibbs sampler, as measured by residual energy decay in 3D spin glass and other benchmarks, is not an explicit function of either the communication clock ($f_{\mathrm{comm}}$) or the local p-bit update clock ($f_{\mathrm{p\text{-}bit}}$) but solely their ratio $n$. There exists a topology- and partition-dependent threshold value of $n$ above which the distributed machine is statistically indistinguishable from a monolithic GPU-based reference. This scaling collapse is a robust property, corroborated across architectures (DSIM-1 and DSIM-2), system sizes (50K–1M p-bits), and problem topologies (regular lattices, Gset Max-Cut, Pegasus/Zephyr graphs, and large irregular 3SAT instances).

When $n$ is reduced below threshold, distributed systems maintain power-law convergence but with a reduced exponent, providing a quantifiable and tunable tradeoff between throughput (sampling speed) and solution quality. Overclocked configurations with intentionally stale boundary states achieve faster times-to-easy-targets but, for sufficiently hard targets, experience crossovers where more conservative, communication-balanced schedules overtake them.

Theoretical Modeling: Universality of the Tradeoff

To separate hardware artifacts from algorithmic properties, the authors implement parallel cluster mean-field theory (CMFT) simulations that precisely mimic the partitioned Gibbs dynamics of the hardware, but on a GPU and with tunably stale boundary averages. The same functional dependency of convergence exponent on the refresh interval is retrieved, up to a monotonic mapping between the number of Monte Carlo sweeps per boundary exchange and $n$. This result establishes the throughput-exponent tradeoff as a generic property of partitioned, parallel stochastic dynamical systems—independent of hardware substrate, random number generation, or arithmetic precision.

Empirical Performance and Benchmark Results

The DSIM-2 system scales to $10^6$ p-bits distributed across 18 high-end FPGAs, performing $\mathcal{O}(10^{12})$ flips/s with all coupling data on-chip. Statistical results align within error bounds with monolithic baselines both for Ising ground state residuals and for practical combinatorial problems, specifically:

• On $L^3=373$ spin glass benchmarks, the DSIM reaches $f_{\mathrm{comm}}$0 residual energy at a rate up to $f_{\mathrm{comm}}$1 faster under overclocking relative to conservative settings.
• On the G81 Max-Cut problem (20,000 spins), the DSIM attains the certified-optimal cut value, with solution statistics matching state-of-the-art heuristic CPU solvers.
• On planted instances from the D-Wave Pegasus/Zephyr graphs (up to 80,800 p-bits), the DSIM achieves the planted ground state.
• The architecture solves a 3SAT instance with $f_{\mathrm{comm}}$2 variables and 250,011 p-bits (via a sparse Ising reduction), satisfying 99.7% of clauses after $f_{\mathrm{comm}}$3 sweeps, with scaling comparable to a reference GPU.

Projected ASIC implementations at the 7nm node suggest that local update bandwidths (up to 100MHz, 0.66 mm$f_{\mathrm{comm}}$4, $f_{\mathrm{comm}}$5250 mW per 8,442-p-bit partition) are not limiting factors; the bottleneck is the bandwidth for boundary exchanges, but required rates are compatible with contemporary die-to-die interconnects such as UCIe and BoW.

Implications and Directions

The results provide a quantitative design rule for scaling stochastic, sampling-based computation: as long as the communication-to-local-update ratio $f_{\mathrm{comm}}$6 exceeds the architecture-dependent threshold (a function of coloring, congestion, and hop-distance via Eq. (2)), parallelism remains algorithmically efficient. This finding directly informs the architecture of future multi-chip, multi-die probabilistic machines—enabling independent local clocks and aggressive scaling independent of monolithic memory limits or power bottlenecks. The universality of the $f_{\mathrm{comm}}$7-controlled tradeoff means that designers can predict and select throughput/accuracy regimes in simulation before investing in hardware implementation.

From a computing systems perspective, probabilistic computing architectures such as the DSIM fundamentally differ from deterministic accelerators. Because the underlying stochastic dynamics are robust to boundary staleness—in the manner of asynchronous Hogwild-style Gibbs sampling—the scaling bottleneck shifts from strict synchrony to a soft tradeoff, opening new flexibilities in architectural choices and system scaling. This robustness is leveraged to extend the envelope of tractable problem sizes for sampling-based inference, optimization, and beyond.

The generality of the partition/communication scaling law should have direct relevance for the integration of nanomagnetic p-bits, monolithic 3D integration, and mesh-based interconnect scaling, and is poised to influence the architectural design of next-generation hardware for inference, sampling, and possibly neural emulation.

Conclusion

This work establishes both a scalable architecture and a quantitative theoretical framework for distributed probabilistic computers with up to one million p-bits, overcoming the single-chip limit. The solution quality and throughput are governed by a single ratio $f_{\mathrm{comm}}$8, universal across hardware and algorithmic parallelization. These insights constitute a concrete basis for future hardware design and system-level scaling of probabilistic machines for large-scale inference and combinatorial optimization.