CMOS-integrated superparamagnetic tunnel junction-based p-bit

Abstract: Probabilistic computers offer promising solutions for computationally hard problems in domains such as combinatorial optimization and machine learning. A key building block in these systems is the probabilistic bit (p-bit), which relies on superparamagnetic tunnel junctions (sMTJs) as its source of randomness. A challenging threshold to cross for scaling sMTJ-based p-bit systems is integration of sMTJs with CMOS technology. In this work, we present experimental results of a p-bit unit cell using sMTJs integrated with 130 nm CMOS technology and demonstrate that the sMTJ's resistance fluctuations can generate a corresponding fluctuating digital output voltage which is tunable via the input voltage. These findings establish the feasibility of CMOS-compatible, sMTJ-based probabilistic circuits and mark a key step toward scalable hardware for real-world probabilistic computing applications.

• The paper demonstrates monolithic CMOS integration of sMTJ-based p-bit cells, achieving bias-tunable stochastic responses and a sigmoid-like transfer across a 0.5V–0.8V range.
• It details a tailored fabrication process using a 130 nm CMOS platform and sMTJ stacks with TMR ratios up to 100% and resistance values between 2.5 kΩ and 8 kΩ.
• The results establish a viable hardware platform for scalable probabilistic computing, addressing integration challenges such as stray fields and via oxidation.

CMOS-Integrated Superparamagnetic Tunnel Junction-Based p-bit: Enabling Scalable Hardware for Probabilistic Computing

Introduction

The integration of superparamagnetic tunnel junctions (sMTJs) with CMOS technology is a fundamental milestone for the hardware implementation of probabilistic computers, which are designed to efficiently tackle computationally intractable problems such as combinatorial optimization and machine learning. This paper ("CMOS-integrated superparamagnetic tunnel junction-based p-bit" (2604.14446)) details the fabrication and characterization of a CMOS-integrated p-bit unit cell based on sMTJs. The demonstrated results provide quantitative insight into the device operation at each integration stage, and establish a practical route for the large-scale deployment of sMTJ-based probabilistic circuits.

Background and Motivation

Probabilistic computing harnesses the stochastic switching behavior of p-bits, which fluctuate between two logic states in response to thermal noise, typically realized by sMTJs with low energy barriers. When mapped to Ising Hamiltonians, these circuits can efficiently sample solution spaces associated with NP-hard problems. Prior demonstrations of large-scale p-computers have relied on FPGAs and externally wired sMTJs, but the lack of BEOL (back-end-of-the-line) integration with CMOS limits scalability, prevents system-level co-integration, and introduces parasitics detrimental to high-density builds. Achieving direct, monolithic integration with CMOS is crucial for practical adoption.

Experimental Methods

A monolithic chip was fabricated using a 130 nm commercial CMOS process in combination with a tailored sMTJ process. The chip includes 150 isolated sMTJs, 240 sMTJs in series with NMOS devices, and 150 fully integrated p-bit unit cells.

The sMTJ stack incorporates a classical Ta/PtMn/Co/Ru/CoFeB/MgO/CoFeB/Ta/Ru/Ta structure, with nominal MgO tunnel barriers and lateral device shapes ranging from 50-80 nm in diameter and aspect ratios between 1 and 4. Post-CMOS, the final encapsulating metal layer was omitted to ensure direct interfacing with via layers, and immediate wafer coating was employed to prevent via oxidation.

The p-bit circuit leverages an sMTJ in series with an NMOS transistor, with the output routed to a variable threshold controller and an inverter, delivering regulated logic levels (ideally 0 V to 1.8 V). The circuit design allows for adjustable channel widths (1, 3, 9, 27 µm) yielding a broad dynamic range.

Results

Standalone sMTJ Characterization

Isolated sMTJs exhibited time-averaged resistance values tunable with applied bias, transitioning from low to high resistance as current and magnetic field were modulated. Measured TMR ratios spanned 50–100%, with low resistance states from ~2.5 kΩ to 8 kΩ. Random telegraph noise signatures corresponded to millisecond-scale thermally activated switching.

sMTJ-NMOS Series and Tunability

Integrated sMTJ-NMOS series devices displayed voltage output swings of approximately 100 mV as the NMOS gate voltage was modulated, demonstrating electrical control of the stochastic switching probability and confirming the suitability for bias-tunable p-bit operation. The window for stochastic operation could be fine-tuned with external magnetic fields or stack engineering to counteract stray fields from the reference layer.

Full p-bit Unit Cell

The completed p-bit cell displayed a bias-dependent output with a robust sigmoid transfer characteristic: as Vbias was swept from 0.5 V to 0.8 V, the time-averaged logic output transitioned from 1.8 V to 0.45 V, providing continuous electrical control over p-bit state occupation. Time-series data at fixed biases corroborated the expected stochastic switching between logic states on nanosecond-to-millisecond timescales.

Notably, the output swing did not reach the ideal 0 V boundary due to observed CMOS non-idealities rather than fundamental circuit limitations, as validated through additional biasing experiments.

Key Numerical Results and Claims

• TMR ratios between 50–100% and low resistance values of 2.5–8 kΩ for the fabricated sMTJs.
• Sigmoid-like transfer behavior of the full p-bit output across a bias range of 0.5–0.8 V, with a dynamic output range from 1.8 V to 0.45 V.
• Voltage swing in sMTJ-NMOS units: 100 mV modulation of output with gate voltage control.
• The device can produce stochastic logic-level outputs at rates determined by the thermal characteristics of each sMTJ, potentially facilitating nanosecond-scale bitstream generation.
• All device non-idealities and integration obstacles (e.g., magnetic stray field, oxidation of vias) are characterized and either mitigated or shown to be non-limiting for integration scale.

Implications and Future Developments

This work enables the direct monolithic integration of sMTJ-based probabilistic elements with CMOS, significantly advancing the scalability and practical deployment of p-bit hardware for applications in intractable optimization and energy-efficient machine learning. By validating the ability to control stochastic device behavior electrically and integrating functional p-bit cells within standard CMOS process lines at 130 nm, this result establishes a hardware platform suitable for further architectural development—namely, large-scale Ising machines and invertible logic engines on silicon.

The demonstrated integration strategy highlights the importance of co-optimization of magnetic stack engineering with advanced CMOS design, especially regarding control of stray fields and minimization of interface roughness. Future investigations should focus on scaling to more advanced nodes, on-chip network topologies for probabilistic inference, and hybrid integration with other emerging devices such as memristors. Additionally, exploration of device-to-device variability, endurance, and large-scale stochastic circuit behavior will be critical for both academic understanding and commercial adoption.

Conclusion

The successful integration and demonstration of CMOS-compatible sMTJ-based p-bits validate these devices as viable stochastic primitives for scalable probabilistic computing. The results quantitatively demonstrate bias-tunable stochastic responses over robust voltage ranges and identify practical integration pathways and physical non-idealities. This work positions sMTJs as a cornerstone technology for the realization of hardware Ising machines, invertible logic, and unconventional computing accelerators poised to address classically intractable computational problems.