AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors (2501.10301v1)

Abstract: The ever-growing scale of data parallelism in today's HPC and ML applications presents a big challenge for computing architectures' energy efficiency and performance. Vector processors address the scale-up challenge by decoupling Vector Register File (VRF) and datapath widths, allowing the VRF to host long vectors and increase register-stored data reuse while reducing the relative cost of instruction fetch and decode. However, even the largest vector processor designs today struggle to scale to more than 8 vector lanes with double-precision Floating Point Units (FPUs) and 256 64-bit elements per vector register. This limitation is induced by difficulties in the physical implementation, which becomes wire-dominated and inefficient. In this work, we present AraXL, a modular and scalable 64-bit RISC-V V vector architecture targeting long-vector applications for HPC and ML. AraXL addresses the physical scalability challenges of state-of-the-art vector processors with a distributed and hierarchical interconnect, supporting up to 64 parallel vector lanes and reaching the maximum Vector Register File size of 64 Kibit/vreg permitted by the RISC-V V 1.0 ISA specification. Implemented in a 22-nm technology node, our 64-lane AraXL achieves a performance peak of 146 GFLOPs on computation-intensive HPC/ML kernels (>99% FPU utilization) and energy efficiency of 40.1 GFLOPs/W (1.15 GHz, TT, 0.8V), with only 3.8x the area of a 16-lane instance.

• The paper introduces a scalable 64-bit RISC-V vector processor design that overcomes interconnect inefficiencies by supporting up to 64 vector lanes.
• The paper achieves 146 GFLOPs performance and 40.1 GFLOPs/W energy efficiency at 1.15 GHz, ensuring high computational throughput for HPC and ML workloads.
• The paper employs a multi-level Global Load-Store Unit with modular vector clusters to demonstrate near-linear scalability with minimal area overhead.

AraXL: Scalable RISC-V Vector Processor for High-Performance Applications

The paper introduces AraXL, a 64-bit RISC-V Vector Processor designed to confront the challenges posed by the growing demand in high-performance computing (HPC) and ML for long-vector processing. AraXL is built to support large-scale data parallelism, leveraging the RISC-V vector extension V 1.0 architecture to achieve significant power, performance, and area (PPA) efficiencies.

AraXL advances current vector processor designs by addressing the physical scalability challenges and interconnect complexities that impede the scaling of vector processors beyond a limited number of lanes. Existing vector processors, even at their largest, demonstrate bottlenecks when dealing with more than 8 lanes while supporting instruction set architectures (ISA) like SIMD. This limitation is largely due to wire-dominant inefficiencies and the costs associated with instruction fetch and decode for long vectors. AraXL circumvents these issues through a distributed and hierarchical interconnect architecture. It is configured to support up to 64 parallel vector lanes, achieving the maximum 64 Kibit per register capacity allowed by the RISC-V V 1.0 ISA.

Performance and Efficiency

AraXL, implemented in a 22-nm technology node, achieves compelling numerical results, including a peak performance of 146 GFLOPs on computation-intensive HPC/ML kernels with over 99% utilization of Floating Point Units (FPUs). Furthermore, it achieves an energy efficiency of 40.1 GFLOPs/W at a frequency of 1.15 GHz under typical conditions (0.8V, 25°C). Compared with a 16-lane instance, the 64-lane AraXL scales the area with a factor of 3.8, demonstrating near-linear scalability in both performance and area.

Architectural Enhancements

The architecture employs several innovative design strategies to enhance scalability and efficiency. AraXL employs a multi-level Global Load-Store Unit (GLSU) to efficiently handle memory-to-vector register file (VRF) mapping, which ensures alignment and shuffling of data across clusters and lanes, minimizing the complexity associated with interconnect design. The cluster architecture, based on modularized vector clusters with scalable interfaces, facilitates efficient data movement with a ring interconnect structure, thereby accommodating up to 64 lanes without latency-induced performance penalties.

Implications and Future Prospects

The successful implementation and evaluation of AraXL indicate that vector processor architectures can be significantly scaled while maintaining efficiency by addressing interconnect challenges and intelligently managing data movement. The research demonstrates the viability of RISC-V V architecture in achieving scalable and energy-efficient solutions for the increasing data parallelism demands in HPC and ML.

The results suggest that future developments in AI could leverage this architecture to further optimize processing capabilities, potentially exploring further granularity in vector lengths or customized optimizations for application-specific integrated circuits (ASICs). AraXL sets a precedence for designing scalable processor architectures that could transform computational efficiency in domains requiring extensive data-level parallelism.

In summary, AraXL offers a sophisticated solution to the current limitations faced by vector processors in handling extensive workloads efficiently, setting a foundation for future advancements in scalable vector processor design within the RISC-V ecosystem.