The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-ready 1.7GHz 64bit RISC-V Core in 22nm FDSOI Technology (1904.05442v1)

Abstract: The open-source RISC-V ISA is gaining traction, both in industry and academia. The ISA is designed to scale from micro-controllers to server-class processors. Furthermore, openness promotes the availability of various open-source and commercial implementations. Our main contribution in this work is a thorough power, performance, and efficiency analysis of the RISC-V ISA targeting baseline "application class" functionality, i.e. supporting the Linux OS and its application environment based on our open-source single-issue in-order implementation of the 64 bit ISA variant (RV64GC) called Ariane. Our analysis is based on a detailed power and efficiency analysis of the RISC-V ISA extracted from silicon measurements and calibrated simulation of an Ariane instance (RV64IMC) taped-out in GlobalFoundries 22 FDX technology. Ariane runs at up to 1.7 GHz and achieves up to 40 Gop/sW peak efficiency. We give insight into the interplay between functionality required for application-class execution (e.g. virtual memory, caches, multiple modes of privileged operation) and energy cost. Our analysis indicates that ISA heterogeneity and simpler cores with a few critical instruction extensions (e.g. packed SIMD) can significantly boost a RISC-V core's compute energy efficiency.

Analysis and Implications of a Linux-Ready 64-bit RISC-V Core in 22nm FDSOI Technology

The paper presents a detailed examination of a 64-bit RISC-V core, named Ariane, fabricated using 22nm FDSOI technology. The research primarily investigates the energy, performance, and efficiency trade-offs associated with a Linux-ready "application-class" processor implementing the RISC-V ISA, particularly focusing on their Ariane core.

Core Architecture and Design

Ariane is an open-source, single-issue, in-order, 64-bit processor designed to support a UNIX-like OS environment by utilizing specific features of the RISC-V ISA. The implementation includes hardware components essential for operating system support, such as a Translation Lookaside Buffer (TLB) and a Page Table Walker (PTW), making it capable of efficiently running Linux. Moreover, the core design supports application-class functionalities such as virtual memory, a feature critical for improved programmability and system security.

The core architecture is configured with a 6-stage pipeline aiming to optimize the balance between clock speeds and critical path lengths. The microarchitecture further integrates advanced components, including an IEEE-compliant floating-point unit (FPU), integer arithmetic logic units, and a branch predictor, covering a wide spectrum of functional operations.

Performance and Efficiency

Ariane demonstrates a peak efficiency of up to 40Gop/sW. The paper reveals the performance metrics obtained through extensive silicon characterization and calibrated post-layout simulations. A significant aspect of this research is the detailed power breakdown which offers insights into the power distribution across various ISA extensions and microarchitectural features. This meticulous analysis enables a clearer understanding of where power is predominantly consumed, such as the instruction and data caches, and TLB operations, which are critical for supporting OS-level functionality.

Furthermore, a comparison in energy efficiency against non-application-class cores emphasizes the additional overhead posed by application-class features. Despite these overheads, the implementation holds its grounds in performance, reporting up to 1.65 DMIPS/MHz, confirming its viability as a scalable processor for a wider range of applications from embedded to server architectures.

Practical and Theoretical Implications

The implications of Ariane's design are multifaceted. Practically, the research underscores the potential for open-source architectures like RISC-V to penetrate areas traditionally dominated by proprietary ISAs, particularly in the burgeoning IoT and AI landscapes where scalability and customization are paramount. The core illustrates how the modularity of the RISC-V ISA can be harnessed to develop efficient, application-class processors in advanced process nodes, while still maintaining a favorable balance between power and performance.

Theoretically, the work contributes to the understanding of design complexities when transitioning from microcontroller to server-class processing, highlighting the energy and area costs associated with sophisticated features like virtual memory and multiprocessing capabilities. This insight can inform design strategies for future processors seeking to bridge the gap between low-power and high-performance systems.

Future Directions in AI and CPU Design

The findings from this paper could steer future research in AI accelerator design, where optimizing for energy efficiency without sacrificing functionality is critical. As AI workloads continue to evolve, the agility offered by reconfigurable ISAs could enable more tailored hardware solutions, potentially influencing decisions in neural network accelerator designs.

Moreover, the continuing development of RISC-V opens an avenue for researchers and developers alike to explore ISA extensions specifically geared towards AI and machine learning applications, potentially yielding more efficient compute capabilities. The open-source nature of Ariane facilitates a platform where such innovations can be collaboratively developed and tested, contributing to an agile and responsive computing landscape.

In conclusion, this paper not only advances Ariane as a competent application-class processor but also pushes the envelope on how open-source ISAs can be effectively leveraged to deliver competitive, efficient, and scalable computing solutions. This work lays a foundation for future explorations in ISA extension and processor architecture design, tailored towards emerging computing challenges.