Optimal circuit realization for MPS-pretrained hardware execution

Determine which circuit realization of an encoded matrix-product state—ladder, mixed-canonical, or brick-wall—is best suited to hardware execution under practical circuit-depth, connectivity, and noise constraints.

Background

Matrix-product states can be mapped to multiple structured parametrized quantum-circuit layouts, including ladder, mixed-canonical, and brick-wall constructions. Although these realizations encode the same type of target state and can use matched two-qubit-block resources, their parallel depths and execution characteristics differ substantially. The paper identifies the hardware-optimal realization as unresolved because prior studies establish MPSs as useful resources for circuit construction without determining which layout is most suitable for noisy hardware execution.