Optimize the GHZ-corridor hardware implementation

Optimize the GHZ-corridor readout and reset path, leakage-removal scheduling, and calibration of dual-use boundary ancillae to reduce the corridor-related logical-error prefactor.

Background

The stitched-code architecture achieves its asymptotic footprint advantage only when errors associated with the GHZ corridors are sufficiently suppressed. The authors identify the corridor prefactor as a central practical limitation and explicitly leave hardware-specific improvements to future development, including readout and reset, leakage-removal scheduling, and calibration of ancillae that alternate between surface-code and corridor functions.