Achieving overparametrization in NISQ-friendly quantum circuits

Ascertain methods to reach overparametrization in noisy intermediate-scale quantum (NISQ) scenarios while accommodating copy complexity constraints, degraded precision scaling, and the difficulty of embedding many independent parameters into practical quantum circuits.

Background

Classical overparametrized models help mitigate poor cost landscapes, turning many local minima into saddle points and improving trainability. Translating this success to quantum circuits is challenging because deep or wide circuits may be needed, which is difficult on near-term hardware and can exacerbate barren plateaus.

Moreover, backpropagation-like training in quantum settings is hindered by the no-cloning constraint. Some approaches reuse a few copies of states to emulate backpropagation, but at the cost of poor precision scaling. These hurdles make it unclear how to practically realize overparametrization in NISQ-friendly circuits.

References

Due to this extra ``copy complexity'', the degraded precision scaling, and the difficulty of squeezing many independent parameters into NISQ quantum circuits, it is currently an open problem to understand how to best reach overparametrization in NISQ-friendly scenarios.

— Myths around quantum computation before full fault tolerance: What no-go theorems rule out and what they don't  (2501.05694 - Zimborás et al., 10 Jan 2025) in Subsection 'Variational quantum algorithms', Subsubsection 'Fundamental limitations of variational quantum algorithms'

It remains a broader question in how quantum models learn to utilise the extra parameters that do not increase the expressivity of the model. And if it's advantageous or detrimental to its learning, such as experiencing double descent or overfitting which are effects found in overparameterising classical models.

— Subspace Controllability in Variational Quantum Circuits: Maximising Expressivity and Increasing Search Efficiency with Dynamical Lie Algebras  (2609.24475 - Barlow et al., 21 Sep 2026) in Section 2.2, “Controllability of the hardware efficient ansatz”