Full integration of data acquisition, STFT, and deep-learning processing on the MPSoC

Determine whether the data-acquisition interface, short-time Fourier transform computation, communication logic, buffering, and Compact ResNet deep-learning accelerator can be fully integrated on the Xilinx Zynq UltraScale+ MPSoC ZCU102 while satisfying resource, placement-and-routing, and timing-closure constraints.

Background

The FPGA implementation demonstrates accelerator-level feasibility for the Compact ResNet, but it uses 93.77% of the available CLB LUTs. The reported deployment relies on a host computer to provide STFT outputs, so the complete onboard acquisition and signal-processing chain has not been integrated or validated.

Although representative STFT and data-acquisition components may fit within the remaining FPGA resources or be partly offloaded to the MPSoC ARM processor, the authors state that a complete system-level resource, placement-and-routing, and timing analysis is still required.

References

Bridging the samples provided from the DAQ to the AXI stream, and buffering/FIFOs for the 32 sample STFT overlap may be possible within the remaining margin, but full integration of the acquisition and STFT subsystems requires a separate resource-budget, placement-and-routing, and timing-closure analysis which remains important future work.

— Deep Learning-Based Detection of Electrical Faults and Power Quality Disturbances in Aerospace Power Systems  (2609.10479 - Guzmán et al., 9 Sep 2026) in Section 5.3, Implementation Results