Experimental verification of end-to-end integrated-system latency

Measure the end-to-end latency of the integrated aircraft power-monitoring system, including sensor acquisition, data transfer, STFT computation, buffering, and Compact ResNet FPGA inference, under representative operating conditions.

Background

The reported latency measures only the neural-network accelerator and its internal data movement, with STFT outputs supplied by a host computer. The authors note that an operational system would additionally include sensors, a data-acquisition card, STFT processing, AXI-stream transfer, and buffering.

Consequently, the measured 6.90-ms mean and 14.40-ms worst-case latencies do not establish the timing behavior of the complete integrated monitoring pipeline. Experimental verification of that end-to-end latency is left unresolved.

References

While experimental verification of an integrated system's latency remains important future work, the cited representative sources claim latencies of those modules would be on the order of microseconds, three orders of magnitude less than the latency of the inference core.

— Deep Learning-Based Detection of Electrical Faults and Power Quality Disturbances in Aerospace Power Systems  (2609.10479 - Guzmán et al., 9 Sep 2026) in Section 5.4, FPGA Inference Performance