Cause of the observed RTL efficiency advantage

Determine whether the greater average power efficiency of RTL-based Transformer inference accelerators on FPGA platforms is caused by the finer control offered by RTL-level design or by the tendency of low-power use cases to favor RTL implementations.

Background

The survey compares FPGA-based Transformer inference accelerators developed using Register-Transfer Level (RTL) and High-Level Synthesis (HLS) tooling. It observes that RTL-based designs generally consume less power on average, while HLS-based designs achieve higher average throughput. However, the comparison is confounded by differences in accelerator architecture, optimization techniques, and application requirements.

The authors explicitly leave unresolved whether the lower power consumption associated with RTL implementations results from the greater low-level control available to RTL designers or from selection effects, namely that low-power applications may be more likely to use RTL. Resolving this issue would clarify whether the observed efficiency advantage is intrinsic to the design methodology or reflects the characteristics of the workloads and use cases studied.

References

While this suggests that RTL-based designs are generally more efficient, the underlying cause is not entirely clear. This trend may either stem from the greater level of control offered by RTL-level design, or from the fact that low-power use-cases are more likely to favour RTL implementations.

— Recent Developments in Transformer Inference Deployment on FPGA Platforms: A Survey  (2609.01212 - Blankestijn et al., 1 Sep 2026) in Section 5.2, subsection “HLS vs RTL”