- The paper introduces a three-stage pipeline that combines hardware-aware NAS, INT4 post-training quantization, and evolutionary CGRA design-space exploration for edge AI accelerators.
- The paper finds that INT4 quantization completely reorganizes the FP32 Pareto frontier, with 0% front survival, a 21.73% dominance-flip rate, and moderate ranking correlation (KT 0.6655).
- The paper shows that FP32-trained surrogates transfer effectively to INT4 search, achieving higher normalized hypervolume than dedicated INT4 surrogates by 12.26% with Random Search and 6.77% with MOEA.
Motivation and problem statement
Edge AI deployment requires architectures that are simultaneously accurate, computationally efficient, and hardware-deployable. Hardware-aware Neural Architecture Search (NAS) addresses this, but existing work splits into two camps: joint quantization-NAS methods (HAQ, APQ, SimQ-NAS, QuantNAS) that fold bit-width selection into the search loop at the cost of expanded search complexity and tight architecture–quantization coupling, and hardware-aware benchmarks such as HW-NAS-Bench that report FP32-only metrics. The simpler NAS-then-quantize strategy — apply Post-Training Quantization (PTQ) after search — has received little analytical attention: the effect of PTQ on the Pareto structure of NAS-discovered architectures is uncharacterised, and no framework combines quantized architecture mapping onto reconfigurable accelerators with automated hardware exploration.
This paper by Mylonas et al. addresses both gaps with two contributions: a three-stage pipeline that maps quantized NAS candidates onto CGRA-based accelerators via evolutionary Design Space Exploration (DSE), and an empirical study of INT4 PTQ's perturbation of the NAS-Bench-201 Pareto space using formal stability metrics computed on ground-truth data for all 15,625 architectures (2608.13293).
The three-stage pipeline
Stage I — hardware-agnostic frontend. A redesign of HW-PR-NAS trains a Pareto rank surrogate on NAS-Bench-201/CIFAR-10 over two objectives (accuracy, FLOPs). The LSTM encoding module is enhanced with a Pool output layer to improve Kendall's Tau (KT) correlation between predicted and true rankings. Random Search (RS) and Multi-Objective Evolutionary Algorithm (MOEA) strategies are guided toward a target FLOPs region, returning ten Pareto-front candidate architectures per run.
Stage II — quantization bridge. Candidates are quantized with Brevitas (INT4 weights/activations, asymmetric, layer-wise), re-ranked in the quantized domain, and filtered; dominated or failing architectures are removed. A feedback loop re-triggers Stage I if no survivors remain. This middleware decouples the model-optimization problem from the accelerator design problem, which is the paper's stated rationale for the NAS-then-quantize approach.
Stage III — hardware-aware backend. Surviving models are mapped onto CGRA4ML-generated Coarse Grain Reconfigurable Arrays via a QONNX-to-QKeras translation layer. The DSE explores PE array rows R∈{8,10,12,16}, columns up to 96, weight SRAM depth, and AXI width under a hard constraint R×C≤MAX_PEs, reducing the space to roughly 1,200 valid configurations. An evolutionary algorithm evaluates candidates against CGRA4ML's free analytical oracle (clock cycles, PE utilization, idle ratio) using a three-term normalized fitness minimizing latency, idle ratio, and area, terminating when fitness improvement falls below 10−4 over eight generations.
PTQ scheme selection
A screening of 325 PTQ configurations without finetuning identified six complexity-robust schemes. Most top performers use 8-bit activations, confirming the strength of INT8 PTQ (e.g., 84.76% Top-1 accuracy for an 8/8 configuration). However, the paper selects a 4/4 asymmetric scheme (26.22% accuracy before finetuning) based on versatility at half of INT8's complexity, noting that a simple two-epoch finetuning restores accuracy from 9.49% to 83.53% — evidence that model information survives aggressive INT4 PTQ. This choice is defensible but notable: the selected scheme is the weakest of the six in raw post-PTQ accuracy, and the finetuning result is demonstrated only on a single baseline architecture.
Quantization sensitivity tracks architectural homogeneity
A key empirical finding links quantization error to model composition. At low computational scales (7–47 MFLOPs), median INT4 accuracy drops reach approximately 5%, with wide interquartile ranges and outliers exceeding 50% degradation. As complexity increases toward 82–220 MFLOPs, the median converges to roughly 0% and variance collapses. The authors attribute this to operation distribution: low-FLOPs cells mix the five NAS-Bench-201 primitives nearly uniformly, where none edges amplify error on remaining paths and skip_connect propagates noise unfiltered, whereas high-FLOPs cells are dominated (~45%) by nor_conv_3x3, whose convolutional lowpass filtering attenuates quantization noise. The implication is direct: quantization fragility is a structural property of the cell composition, not merely of scale, so FP32 Pareto fronts populated by heterogeneous sparse cells are disproportionately destabilized under INT4.
Pareto stability under INT4: full reorganization, preserved global ranking
The stability analysis yields a strikingly mixed picture. On one hand, the Pareto front survival rate is 0% — every FP32 Pareto-optimal architecture leaves the efficient frontier after INT4 quantization — and the dominance flip rate is 21.73%, meaning roughly one in five FP32 dominance relationships breaks. Ground-truth KT correlation between FP32 and INT4 rankings is 0.6655, indicating moderate but real reordering. Pareto rank sensitivity of 0.2404 shows quantization fragility is largely independent of FP32 Pareto optimality.
On the other hand, the migrated FP32 front closely tracks the ground-truth INT4 front, and surrogate transferability metrics support zero-shot transfer:
| Metric |
Value |
| KT (original FP32) |
0.8352 |
| KT (zero-shot transfer to INT4) |
0.7219 |
| KT (fine-tuned on INT4 data) |
0.8219 |
The narrow gap between zero-shot and fine-tuned transfer suggests the ranking landscape is sufficiently preserved to make surrogate retraining unnecessary.
This hypothesis is validated by search experiments averaged over 50 runs under a 0.625–10 MFLOPs budget. The FP32 zero-shot surrogate achieves higher normalized hypervolume than a dedicated INT4-trained surrogate under both RS (+12.26%) and MOEA (+6.77%), while accuracy differences fall within one standard deviation. The authors attribute this counterintuitive result to the cleaner, less noisy FP32 training signal combined with substantial cross-precision Pareto correlation; they also observe the INT4 surrogate biases toward high-FLOPs architectures, underrepresenting the low-FLOPs region that hypervolume rewards. The practical implication is significant: practitioners need not invest in quantized-data surrogate training for INT4-class PTQ, despite the complete turnover of the Pareto front itself.
Hardware DSE results
For three surviving Pareto architectures, the DSE converges to the same optimal CGRA configuration — a 16×66 PE array with weight SRAM depth 576, clocked at 250 MHz — reflecting their shared profile of nor_conv_1x1 and skip_connect operations across ~15 cell recurrences. Cycle counts range from 53,605 to 118,690, with the outlier attributable to a single nor_conv_3x3 at the first cell node amplifying per-cell workload across all recurrences. PE utilization sits around 41–46%. The convergence of all three architectures to one configuration suggests the DSE landscape is dominated by shared structural features rather than per-model idiosyncrasies, though the evaluation covers only three survivors from a single search run.
Limitations and open questions
Several constraints bound the generality of these findings. The empirical study is confined to NAS-Bench-201 on CIFAR-10 with uniform INT4 PTQ; the authors explicitly defer more complex mixed-precision schemes to future work, and it remains open whether the zero-shot transfer advantage persists when bit-width varies per layer or when quantization-aware training is applied. The INT4 scheme was selected partly on the basis of a single baseline architecture's finetuning behavior, and the 0% front survival rate is measured against CIFAR-10 accuracies rather than deployment-relevant hardware latencies, which HW-NAS-Bench-style targets would provide. The Stage I surrogate redesign reports improved KT but the paper does not isolate its contribution from other pipeline components. Finally, the DSE relies on CGRA4ML's analytical oracle without RTL-level validation of the reported cycle counts, and the identical optimal configuration across all tested models raises the question of whether the explored parameter ranges are too coarse to differentiate structurally similar survivors.
Conclusion
The paper delivers a deployable NAS-to-CGRA pipeline and a full-scale empirical characterization of INT4 PTQ's effect on the NAS-Bench-201 Pareto space. Its central result is a tension worth noting: INT4 quantization completely reorganizes the efficient frontier (0% survival, 21.73% dominance flips), yet the FP32-trained surrogate transfers effectively zero-shot and even outperforms a dedicated INT4 surrogate in hypervolume coverage. For edge deployment workflows, this supports decoupled NAS-then-quantize designs with FP32 surrogates, provided downstream filtering accounts for the front instability the study documents.