Synthesize and experimentally validate the FPGA implementation

Synthesize and experimentally validate the Meta2L algorithm for stateful STAR-RIS optimization on the target Xilinx Zynq UltraScale+ MPSoC device, including measurement of its actual hardware latency beyond the analytical cycle-count estimate.

Background

The paper estimates Meta2L’s critical-path latency by analytically mapping arithmetic operations to DSP48E2 resources on a Xilinx Zynq UltraScale+ MPSoC. Under the stated assumptions, the warm-start path is estimated to fit within the channel coherence window.

However, the estimate assumes that data remain on-chip, that sufficient parallel multipliers are available, and that only arithmetic cycles contribute to latency. It does not include CSI acquisition, the AP-to-surface control-link delay, or implementation effects that would be revealed through hardware synthesis and measurement. Consequently, an actual implementation has not yet established whether the reported latency margin is achievable on the target device.