Evaluate Clifford deformation under more precise circuit-level biased-noise models

Evaluate the performance of the Chameleon calibration-aware Clifford-deformation compiler under a more precise biased-noise model for superconducting hardware, particularly one incorporating bias in noise components beyond idle errors, to determine whether its circuit-level logical-error-rate gains change.

Background

The paper evaluates Chameleon primarily with a phenomenological error model and supplements this analysis with Stim’s Si1000 circuit-level noise model. In the latter experiment, only the idle-error component is biased using a model derived from Google Willow calibration data, while the remaining circuit-level noise components are uniform. The authors report smaller gains than under the phenomenological model and explain that the resulting overall bias is weak.

The unresolved issue is whether Chameleon would exhibit different performance under a more precise circuit-level biased-noise model that more faithfully represents superconducting hardware. The authors state that evaluating such a model requires access to actual superconducting hardware, which they do not have, and explicitly leave this direction for future work.