Balancing Soft NoC Flexibility with Hardened Components on FPGAs

Determine principled methodologies for balancing the flexibility and customization capabilities of FPGA soft Networks-on-Chip implemented in programmable logic (e.g., Vivado AXI SmartConnect and AXI4-Stream Switch) with the performance, routability, and resource-efficiency advantages of hardened Network-on-Chip components integrated in silicon (e.g., AMD Versal NMUs/NSUs/NPS), particularly in large multi-die FPGA systems where cross-SLR communication and diverse traffic patterns impose competing constraints.

Background

The paper systematically characterizes performance trade-offs between soft and hardened NoCs on AMD Versal FPGAs, showing that hardened NoCs reduce resource use and improve frequency, especially across SLR boundaries, but can suffer throughput penalties under certain traffic patterns and placements. These observations highlight complex design decisions around where and how to deploy soft versus hardened interconnects.

Within the broader context of FPGA NoCs, prior work and the authors identify an unresolved challenge: how to balance the flexibility of soft NoCs—valuable for application-specific customization and dynamic behaviors—with the efficiency and robustness of hardened NoC components. This balance is particularly difficult in multi-die devices with non-uniform vertical and horizontal interconnect characteristics, making it a persisting open question for design methodology and tooling.