Conductance scaling and power comparison for FLAS

Determine how to introduce adjustable conductance scaling into the factorized low-rank approximation scheme (FLAS) to enable power control, and determine whether FLAS consumes less power than baseline vector–matrix multiplication.

Background

The paper extends the previously proposed factorized low-rank approximation scheme (FLAS) for memristor-based vector–matrix multiplication by incorporating adjustable column-wise conductance scaling. The earlier FLAS formulation improved computation accuracy through low-rank factorization and stage-wise averaging but did not address conductance scaling or power consumption.

The authors explicitly identify two unresolved issues motivating the present study: how conductance scaling can be incorporated into FLAS to make power control possible, and whether the resulting FLAS implementation consumes less power than the directly implemented baseline VMM scheme. The paper subsequently develops analytical MSE and power expressions and numerically investigates these comparisons, so the unresolved formulation in the introduction serves as the stated motivation rather than a separate conjecture.