Power-MSE trade-off of Factorized Low-rank Approximated Computation Scheme with Memristors

Abstract: Memristor crossbars enable analog vector-matrix multiplication (VMM) which is promising for machine learning applications. Scaling matrix entries to lower memristor conductance levels reduces power consumption but increases the impact of memristor programming noise on VMM accuracy. To investigate how low-rank factorization can improve this trade-off, we extend the previously proposed factorized low-rank approximation scheme (FLAS) to support adjustable conductance scaling. We then derive closed-form MSE and power expressions for both FLAS and baseline VMM. Based on these expressions, we establish an analytical power-MSE trade-off framework to capture the coupled effects of approximation rank, replication allocation, and conductance scaling under constraints on memristor count and conductance scaling bounds. Numerical results demonstrate FLAS's power-MSE advantage across matrices with different singular value spectra. The power decomposition explains how TIA feedback resistance affect this advantage.