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Quantify overhead of dynamic DSU way repartitioning and compare to page coloring

Determine the runtime overhead incurred by frequently reconfiguring Arm DSU L3 cache way groups via the CLUSTERPARTCR register to support task-level cache isolation within a scheduler, and compare this overhead to the overhead of software set partitioning via page coloring, in order to assess which approach is preferable for dynamic, scheduling-level interference management.

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Background

The paper focuses on inter-core interference and evaluates way and set partitioning at the last-level cache. It proposes extending cache partitioning to scheduler-level task isolation, which would require dynamic reconfiguration of DSU way groups (via CLUSTERPARTCR) and/or dynamic page coloring.

While DSU way-partitioning can be modified at runtime, the cost of frequent repartitioning has not been characterized. Establishing this overhead and comparing it against the cost of dynamic page coloring is necessary to guide the design of real-time schedulers that leverage cache partitioning for temporal isolation.

References

While way-partitioning can be dynamically adjusted by modifying the {CLUSTERPARTCR} register, the potential overhead of frequent changes has not been studied. Future work should assess whether this overhead is lower than the one incurred in set-partitioning.

— Arm DynamIQ Shared Unit and Real-Time: An Empirical Evaluation (2503.17038 - Pradhan et al., 21 Mar 2025) in Section 6 (Conclusion and Future Directions)