Virtual Atom Intermediate Representation (VAIR)

• Virtual Atom Intermediate Representation is a hierarchical model that treats logical registers as 'virtual atoms' to support level-wise compilation in concatenated quantum error correction codes.
• It addresses compilation overhead and cascading latency amplification by preserving both legal executability and parallelism across multiple concatenation levels.
• By aligning logical operations with neutral atom geometric constraints through a recursive tensor-product mapping, VAIR significantly boosts scheduling efficiency and reduces spacetime overhead.

Searching arXiv for the cited paper and closely related neutral-atom compiler context. Searching arXiv for "ConiQ Enabling Concatenated Quantum Error Correction on Neutral Atom Arrays". Virtual Atom Intermediate Representation (VAIR) is a hierarchical intermediate representation introduced in ConiQ, a hardware-aware quantum compiler designed to compile fault-tolerant quantum circuits for neutral atom arrays using concatenated quantum error correction, specifically many-hypercube codes (Liu et al., 7 Aug 2025). VAIR models logical registers at higher concatenation levels as “virtual atoms,” extending the neutral-atom execution model from level 0 to all concatenation levels so that compilation can proceed level by level while preserving both legal executability and parallelism. Within this formulation, VAIR sits between the logical circuit and the physical hardware: it is neither merely a logical circuit IR nor a full physical layout, but a multi-level geometric register model.

1. Problem setting and rationale

VAIR was introduced to address two practical bottlenecks identified for concatenated codes. The first is logical-gate overhead, especially for individually addressable logical $CNOT$ operations. Prior work relied on distillation-based methods for addressable logical gates, and these methods recursively consume many lower-level resource states, causing exponential spacetime overhead as concatenation depth grows (Liu et al., 7 Aug 2025).

The second bottleneck is compilation overhead and loss of parallelism when targeting neutral atom arrays. Existing compilers such as Atomique and Enola flatten the circuit and code structure too early, effectively unfolding everything to the physical level before mapping and scheduling. According to the ConiQ formulation, this ignores the hierarchical organization of concatenated codes and makes it difficult to exploit batched logical operations. The paper further distinguishes two failure modes: legalization-first compilation schedules sequentially so everything is legal but loses the hardware’s parallelism, whereas optimization-first compilation batches all independent gadgets for parallelism but may fail physical legality. The resulting phenomenon is termed cascading latency amplification, meaning that inefficiency at one level multiplies through higher concatenation levels (Liu et al., 7 Aug 2025).

In this context, VAIR is introduced as a hierarchical and constraint-aware compiler abstraction. Its purpose is to make the representation itself compatible with the nested structure of concatenated codes and with the constrained, row/column-addressable, move-enabled execution model of neutral atom hardware. A plausible implication is that the IR is not a passive data format but the mechanism through which optimization and legalization are made compatible.

2. Core abstraction and state semantics

Conceptually, VAIR stands for Virtual Atom Intermediate Representation. Its central idea is that logical registers at concatenation level $l$ are treated using the same style of state, instruction, and constraint model as physical atoms on neutral atom hardware, except that the “atoms” at level $l$ are registers from level $l-1$ (Liu et al., 7 Aug 2025). This recursive interpretation is the basis for the term virtual atoms.

The VAIR state at level $l$ is defined as the four-tuple

$\mathcal{R}^l=(I, J, A, S)$

where $I$ denotes the ordered $x$-coordinates of AOD registers, $J$ denotes the ordered $y$-coordinates of AOD registers, $l$0 is the register index at AOD position $l$1, or $l$2, and $l$3 is the register index at SLM position $l$4, or $l$5 (Liu et al., 7 Aug 2025).

This mirrors the physical-state model introduced for neutral atom arrays, but reinterprets it one abstraction level higher. At each concatenation level, the representation includes a program state, an instruction set, and the same ordering and addressability constraints, but interpreted at the appropriate level. This suggests that VAIR is designed to preserve machine-like semantics across concatenation levels rather than postponing physical realism until the final lowering stage.

3. Register geometry and instruction model

VAIR is organized around a geometric register model. At each level, SLM registers live on a unit integer grid, AOD registers occupy movable positions with ordered coordinates, the program state records which register is where, and instructions operate on registers using the same kinds of neutral-atom operations (Liu et al., 7 Aug 2025).

The level-$l$6 instruction set is given as follows:

Instruction	Role
$l$7, $l$8	transfer between AOD and SLM
$l$9	move AOD registers
$l$0	apply a single-register gadget $l$1
$l$2	apply a two-register gadget $l$3 to overlapping pairs

This instruction model is the central abstraction of VAIR. Logical operations and register placements are expressed in a form that resembles the physical machine, but recursively one level up. The representation therefore preserves both the nested structure of concatenation and the row-column constraints characteristic of neutral atom execution. In the terminology of the paper, VAIR is the abstraction that allows ConiQ to compile “level by level” while retaining executability and batching opportunities.

4. Register mapping and hierarchical lowering

A key technical component of VAIR is its register-mapping rule. For a level-$l$4 register with subregister coordinates $l$5, the $l$6-th subregister of a register at position $l$7 maps to

$l$8

where

$l$9

and the paper summarizes this using tensor products: $l-1$0 with an analogous construction for $l-1$1 (Liu et al., 7 Aug 2025).

This tensor-product view provides the mechanism by which a high-level register layout is systematically expanded into a lower-level layout. VAIR then defines recursive lowering rules such that $l-1$2 lowers to $l-1$3, $l-1$4 lowers to $l-1$5, $l-1$6 lowers by decomposing $l-1$7 into lower-level gadgets and applying them to tensor-expanded coordinates, and $l-1$8 lowers analogously for two-register gadgets (Liu et al., 7 Aug 2025).

The stated invariant is that if the high-level instruction obeys VAIR constraints, its lower-level expansion does too. This is the formal basis for the claim that a schedule legal in VAIR at level $l-1$9 is guaranteed to lower to a legal schedule at level 0. The paper also states that hierarchical lowering introduces no extra overhead, making the lowering stage not merely recursive but constraint-preserving and cost-preserving in the intended sense.

5. Optimization, batching, and legalization

VAIR is the substrate for what ConiQ terms static inter-level optimization. The compiler flow has three phases: logical-to-gadget transformation, static inter-level optimization using VAIR, and hierarchical lowering. In the first phase, the logical circuit is converted into top-level fault-tolerant gadgets, and AHA logical $l$0 gates are used for efficient logical $l$1 operations. In the second phase, VAIR is used to generate optimized register mappings and schedules at each concatenation level. In the third phase, the optimized high-level VAIR schedule is recursively lowered to the next level and eventually to native neutral atom operations (Liu et al., 7 Aug 2025).

The practical optimization mechanism within VAIR is Algorithm 1: Greedy Scheduling of Lower-Level Instructions. Its workflow is described as follows: start with a sequence of lower-level instructions implementing a higher-level gadget; repeatedly extract the current front layer of instructions with no dependencies; randomly select an instruction type; find the maximal addressable set satisfying the row-column constraint; generate a batched VAIR instruction from that set; append it to the schedule and remove scheduled instructions; and continue until done (Liu et al., 7 Aug 2025).

This algorithm is significant because it addresses the methodological tension identified earlier. Legalization-first destroys parallelism, and optimization-first can produce illegal schedules. VAIR instead exposes the hardware constraints already at each logical level, so batched execution is constructed within the legality model rather than repaired afterward. The paper states two corresponding guarantees: level-wise legalization ensures global legalization, and level-wise optimization ensures global optimization. Improvements made at a higher level therefore propagate downward and directly reduce physical execution cost.

6. Architectural role, examples, and reported implications

Within ConiQ, VAIR is the core abstraction that makes the second and third compilation phases possible. The paper characterizes it as a template-like language for compiling one level into the next without losing addressability, legality, batching opportunities, or the nested structure of concatenation. It also emphasizes that ConiQ can reuse optimized templates produced at one level when compiling the next, and identifies this reuse as a major contributor to the reported compilation-time speedup (Liu et al., 7 Aug 2025).

The paper provides a concrete example with $l$2. Level-0 physical qubits are grouped into level-1 registers, and two columns of level-1 logical qubits are then encoded again into a level-2 register. A logical $l$3 on the first logical qubit of a level-2 register decomposes into two level-1 $l$4 operations, each of which further decomposes into four physical $l$5 operations. Additional examples include mapping four level-1 registers to their constituent level-0 registers, a level-1 gadget implemented by level-0 gadgets, and a level-1 movement implemented by level-0 movements. These examples show that VAIR is not only descriptive but a recursive compilation framework.

VAIR is presented as complementary to Automorphism-assisted Hierarchical Addressing (AHA) logical $l$6 gates. AHA supplies the logical-gate mechanism, especially efficient individually addressable logical $l$7 operations, whereas VAIR supplies the compilation substrate that maps, schedules, and lowers those logical gadgets efficiently. The paper states that ConiQ achieves up to $l$8 reduction in spacetime overhead and up to $l$9 reduction in compilation time compared to state-of-the-art compilers, with AHA gates providing an additional overhead reduction of up to $\mathcal{R}^l=(I, J, A, S)$0. It further reports spacetime overhead reductions up to $\mathcal{R}^l=(I, J, A, S)$1 from VAIR-related scheduling improvements alone at level 4, and notes that VAIR is especially effective at higher concatenation levels, where naïve compilation would suffer from cascading overhead (Liu et al., 7 Aug 2025).

Taken together, these results position VAIR as the mechanism through which concatenated codes are compiled without flattening away their hierarchy. The paper’s bottom-line characterization is that VAIR is a hierarchical, constraint-preserving intermediate representation that treats logical registers in concatenated QEC codes as virtual atoms arranged and manipulated using neutral-atom-like state and instruction semantics. In that role, it is the component of ConiQ that enables level-wise mapping, scheduling, legalization, and lowering while preserving legality and parallelism across concatenation levels.