Automorphism-assisted Hierarchical Addressing (AHA)

• Automorphism-assisted Hierarchical Addressing (AHA) is a gate-construction scheme that leverages code automorphisms to isolate specific logical qubits with minimal overhead.
• It employs hierarchical refinement by applying automorphism-induced permutations and batched transversal gates across multiple concatenation levels.
• AHA enables practical, addressable logical CNOT gates on platforms such as neutral atom arrays while maintaining fault tolerance and space efficiency.

Automorphism-assisted Hierarchical Addressing (AHA) is a gate-construction scheme for concatenated quantum error-correcting codes that exploits code automorphisms at every concatenation level to make specific logical qubits addressable with low overhead. In the many-hypercube setting, where each register encodes multiple logical qubits and transversal operations are naturally applied in batched form across an entire block, AHA enables the selection of a chosen subset—and ultimately a single logical qubit—by composing automorphism-induced permutations with batched gates level by level. In "ConiQ: Enabling Concatenated Quantum Error Correction on Neutral Atom Arrays" (Liu et al., 7 Aug 2025), AHA is introduced as the mechanism that makes individually addressable logical CNOT gates practical on neutral atom arrays without resorting to costly distillation.

1. Formal definition and coding-theoretic setting

AHA is defined in the context of stabilizer codes and their automorphism groups. Let $C$ be an $[[n,k,d]]$ stabilizer code with physical-qubit coordinates indexed by $[n]=\{1,\dots,n\}$ and stabilizer group $S \subset P_n$, where $P_n$ is the $n$-qubit Pauli group. An automorphism of $C$ is a permutation of coordinates that maps the code to itself, namely a permutation $\pi \in S_n$ such that the induced action on Pauli operators preserves the stabilizer group:

$\mathrm{Aut}(C)=\{\pi \in S_n \mid \pi(S)=S\}.$

Operationally, such a permutation re-labels physical qubits while preserving logical operators up to relabeling (Liu et al., 7 Aug 2025).

The scheme is instantiated for many-hypercube codes built from the error-detecting family $D_{2m}$. For this family, $[[n,k,d]]$0 contains permutations that exchange the logical operators of pairs of encoded logical qubits. The data specifies that these automorphisms can be realized by physical SWAPs of selected qubit pairs or, at higher concatenation levels, by batched SWAPs of entire rows or columns of the register layout. This property is the algebraic basis for addressability in AHA.

The relevant base codes are $[[n,k,d]]$1 CSS codes with stabilizers

$[[n,k,d]]$2

Two concrete instances are emphasized: $[[n,k,d]]$3, the $[[n,k,d]]$4 code encoding $[[n,k,d]]$5 logical qubits in $[[n,k,d]]$6 physical qubits, and $[[n,k,d]]$7, the $[[n,k,d]]$8 code encoding $[[n,k,d]]$9 logical qubits in $[n]=\{1,\dots,n\}$0 physical qubits. The paper uses $[n]=\{1,\dots,n\}$1 as the core of many-hypercube constructions (Liu et al., 7 Aug 2025).

2. Hierarchical addressing in concatenated many-hypercube codes

AHA operates on an $[n]=\{1,\dots,n\}$2-level concatenated code

$[n]=\{1,\dots,n\}$3

with logical coordinates labeled by multi-indices $[n]=\{1,\dots,n\}$4. The essential mechanism is hierarchical refinement. At each level $[n]=\{1,\dots,n\}$5, one chooses an automorphism $[n]=\{1,\dots,n\}$6 that permutes subregisters along a designated dimension, such as swapping the lower and upper half of a register. The composed map

$[n]=\{1,\dots,n\}$7

reshapes the logical layout so that the desired logical qubit lies in the selected half at every level (Liu et al., 7 Aug 2025).

The data describes this procedure as a successive refinement of a selection mask: from half of the logical qubits, to a quarter, and so on, until a single target logical qubit is isolated. At each refinement stage, automorphism-induced permutations are interleaved with batched transversal gates. Because the many-hypercube register structure is organized as small, nearly hypercube-like grids—such as a $[n]=\{1,\dots,n\}$8 footprint for $[n]=\{1,\dots,n\}$9 or a $S \subset P_n$0 footprint for $S \subset P_n$1—the required permutations can be implemented in a locality-compatible manner.

The many-hypercube construction itself is described as space-efficient because it starts from minimal error-detecting codes with high encoding rates and composes them by concatenation. A four-level construction yields an encoding rate $S \subset P_n$2 and distance about $S \subset P_n$3, which is described in the paper’s discussion as “encoding 1 logical qubit using $S \subset P_n$4 physical qubits on average” (Liu et al., 7 Aug 2025). This suggests that AHA is not merely a gate-synthesis technique, but is closely tied to the architectural premise that many-hypercube codes retain high rate even after several concatenation levels.

3. Gate mechanism for addressable logical CNOT

AHA implements addressable logical CNOT using three ingredients: automorphism-induced intra-register permutations, batched transversal gates enabled by CSS structure, and hierarchical refinement of selection using ancillas in a “bridge gate” style (Liu et al., 7 Aug 2025).

For CSS codes, including $S \subset P_n$5, transversal CNOT between two registers applies physical CNOTs pairwise to corresponding coordinates and induces logical CNOT across corresponding logical qubits. In the absence of additional structure, this transversality is naturally batched: every matched logical pair is acted on simultaneously. AHA converts this all-to-all paired action into an addressable action on a chosen logical pair.

Within a register, the automorphism group supplies the intra-register permutations needed for selection. In $S \subset P_n$6, swapping selected physical qubits exchanges the two logical qubits, constituting a logical SWAP. By swapping other coordinate pairs, one can also implement logical CNOT between the two encoded qubits. At higher levels, these become dimension-wise batched permutations, such as row or column swaps, which yield batched logical CNOT gates across half the logical qubits within a register.

Across registers, the procedure begins with an inter-register batched CNOT: a transversal CNOT over all corresponding coordinates realizes CNOT on all corresponding logical pairs. To isolate a subset, ancilla registers are used in conjunction with the “bridge-gate” idea. After suitable batched SWAPs $S \subset P_n$7 along a chosen dimension, the target subset is arranged to occupy a designated half of the register. A CNOT is then executed only on that half. Repeating this binary partitioning across levels isolates a single logical qubit, after which the desired logical CNOT is performed and the permutations are undone (Liu et al., 7 Aug 2025).

Because permutations and batched operations can propagate faults, AHA inserts EC cycles to maintain fault tolerance. The data states that SWAPs and transversal CNOTs are constant-time and locality-compatible on the neutral-atom hardware, so the overall AHA depth is dominated by a few EC cycles at each refinement step. This is the basis of