QCrank: Quantum Data Encoding Scheme

• QCrank is a quantum-parallel, vectorized encoding scheme that loads m2^n (or n_d2^(n_a)) real values into n+m qubits, enabling structured data storage.
• It employs uniformly controlled R_y rotations on a superposed address register to perform hardware-friendly, parallel data ingestion on NISQ devices.
• The design supports address-synchronous readout and efficient integration with DPQA architectures and frameworks like Monarq for sequence and image transformations.

QCrank is a quantum-parallel, vectorized data-encoding scheme for storing sequenced real-valued classical data in a quantum state by combining an address register in uniform superposition with address-conditioned single-qubit rotations on a data register. Across the literature, it is presented as a compact, structured, NISQ-compatible method for loading $m2^n$ or, equivalently, $n_d2^{n_a}$, real values into $n+m$ or $n_a+n_d$ qubits, while preserving addressability through conditional measurement of data-qubit observables (Balewski et al., 2023). Subsequent work treats QCrank both as a compilation target for neutral-atom dynamically programmable qubit arrays (DPQAs) and as the data-ingestion layer of the Monarq framework, where it is composed with EHands for sequence and image transformations on near-term devices (Balewski et al., 14 Jul 2025, Balewski et al., 3 Mar 2026).

1. Definition and representational model

In the original formulation, QCrank is a quantum-parallel vectorized classical-data encoding based on uniformly controlled rotations. It is designed for the practical quantum data-loading problem: encoding classical real values into a quantum register in a form that is structured, hardware implementable on NISQ devices, parallel over many input entries, and useful for downstream quantum computation (Balewski et al., 2023).

The scheme partitions the register into address qubits and data qubits. Using the notation of the DPQA compilation study, QCrank employs $n_a$ address qubits and $n_d$ data qubits, with storage capacity

$L = n_d \cdot 2^{n_a}.$

Each data qubit stores one sequence, each sequence has length $2^{n_a}$, and the address register selects the position within the sequence. Thus QCrank stores $n_d$ sequences of length $2^{n_a}$, for a total of $n_d2^{n_a}$0 real values in $n_d2^{n_a}$1 (Balewski et al., 14 Jul 2025). In the notation of the earlier paper, the same capacity is written as $n_d2^{n_a}$2, where $n_d2^{n_a}$3 is the number of address qubits and $n_d2^{n_a}$4 is the number of data qubits (Balewski et al., 2023).

The data are indexed as $n_d2^{n_a}$5 or $n_d2^{n_a}$6, where the address index $n_d2^{n_a}$7 ranges over $n_d2^{n_a}$8 and the channel index $n_d2^{n_a}$9 ranges over $n+m$0. The 2025 DPQA paper gives the encoded state in a typeset-damaged form, but its intended meaning is explicit: for each address basis state $n+m$1, the data register is prepared as a tensor product over data qubits, with amplitudes determined by the corresponding encoded values $n+m$2 (Balewski et al., 14 Jul 2025). The 2023 paper gives the same structure more cleanly as

$n+m$3

with $n+m$4 (Balewski et al., 2023).

A recurring interpretation across the papers is that QCrank behaves like a quantum random-access structured encoding of a table of real numbers indexed by address and channel. This does not mean random access in the classical memory sense; rather, it means that the address register labels which entry is being referred to, while the data qubits encode the associated values (Balewski et al., 3 Mar 2026).

2. Encoding map, circuit construction, and decoding semantics

QCrank constructs the encoded state by first preparing the address register in uniform superposition with Hadamards and then applying one uniformly controlled rotation per data qubit. In the 2023 formulation, each data-qubit unitary is

$n+m$5

and the full encoding unitary is the product of these $n+m$6 operators applied after $n+m$7 on the address register (Balewski et al., 2023).

The 2025 DPQA study emphasizes that QCrank uses uniformly controlled rotations, specifically single-qubit $n+m$8 rotations, interspersed with entangling gates, and exploits superposition over the address qubits so that one data qubit can represent multiple values depending on the address state. It further states that the actual implemented $n+m$9-rotation angles are not the raw data values but Walsh-Hadamard-transformed parameters,

$n_a+n_d$0

so the encoded data are synthesized through a Walsh-Hadamard transform over the address index (Balewski et al., 14 Jul 2025).

The Monarq paper describes the same representational layer through EVEN expectation-value encoding. There each scalar $n_a+n_d$1 is encoded by

$n_a+n_d$2

with the operational relation

$n_a+n_d$3

chosen so that the expectation value of $n_a+n_d$4 equals $n_a+n_d$5 (Balewski et al., 3 Mar 2026). This gives QCrank a particularly direct decoding semantics: a stored value is recovered from the conditional $n_a+n_d$6-expectation value of the relevant data qubit.

The readout model is therefore not tomography of a high-dimensional amplitude vector. The 2025 paper describes decoding operationally: measure a selected data qubit, interpret the result as a $n_a+n_d$7-basis expectation value, and simultaneously measure the address qubits so that the measured address bitstring specifies which sequence position was read (Balewski et al., 14 Jul 2025). The 2026 paper makes this explicit with

$n_a+n_d$8

where $n_a+n_d$9 is the conditional probability of observing $n_a$0 on data qubit $n_a$1 given address $n_a$2 (Balewski et al., 3 Mar 2026). The 2023 paper gives the equivalent relations

$n_a$3

together with the inverse reconstructions $n_a$4 or $n_a$5, depending on the preprocessing convention (Balewski et al., 2023).

A central property of this design is that the encoded data live in local expectation values of the data qubits conditioned on address, rather than in arbitrary amplitudes requiring global state reconstruction. The 2026 paper identifies this as the reason QCrank composes cleanly with EHands and remains practical for NISQ readout (Balewski et al., 3 Mar 2026).

3. Scaling properties, storage density, and measurement cost

QCrank’s principal compactness claim is that it represents $n_a$6 real parameters using only $n_a$7 qubits, or $n_a$8 values using $n_a$9 qubits. This is the main storage-density relation appearing in both the original paper and the DPQA case study (Balewski et al., 2023, Balewski et al., 14 Jul 2025).

The 2025 paper gives a particularly concrete resource characterization. For a QCrank circuit with $n_d$0 address qubits and $n_d$1 data qubits, the number of single-qubit $n_d$2 gates and the number of two-qubit entangling gates are both

$n_d$3

Under the assumption that $n_d$4 is divisible by $n_d$5, the circuit depth is estimated as

$n_d$6

with a parallelism factor of $n_d$7 (Balewski et al., 14 Jul 2025). This depth expression is specific to the structured compilation strategy discussed այնտեղ and is significant because it exposes layers of entangling operations that can be parallelized up to the address-register width.

The earlier paper states the same asymptotic point more generally: logical state-preparation complexity scales as $n_d$8, which is natural when all $n_d$9 classical parameters are independent, since the circuit must incorporate each of them (Balewski et al., 2023). The Monarq paper adds that parallel uniformly controlled rotation implementation reduces CNOT depth by up to a factor of $L = n_d \cdot 2^{n_a}.$0 compared with serial implementations, a claim made in the context of NISQ suitability (Balewski et al., 3 Mar 2026).

The compactness of the qubit representation does not remove the cost of classical recovery. The 2023 paper states that reconstructing all encoded values requires estimating conditional statistics for every address and data-qubit pair; since each address occurs with probability $L = n_d \cdot 2^{n_a}.$1, total shots must scale at least linearly with $L = n_d \cdot 2^{n_a}.$2 to maintain fixed precision per address sector (Balewski et al., 2023). The 2025 study operationalizes this point by scaling shots with $L = n_d \cdot 2^{n_a}.$3 so that statistical error remains roughly constant across problem sizes, using totals of $L = n_d \cdot 2^{n_a}.$4, $L = n_d \cdot 2^{n_a}.$5, or $L = n_d \cdot 2^{n_a}.$6 shots depending on configuration (Balewski et al., 14 Jul 2025). The 2026 Monarq paper reports substantially larger shot counts for some application circuits, ranging from $L = n_d \cdot 2^{n_a}.$7 to $L = n_d \cdot 2^{n_a}.$8 million shots depending on the task (Balewski et al., 3 Mar 2026).

A common misconception is therefore that QCrank’s exponential storage density implies exponential compression of end-to-end classical I/O. The published analyses point in the opposite direction: QCrank compresses the in-register representation, but full classical recovery remains measurement intensive (Balewski et al., 2023).

4. Hardware realization and DPQA-oriented compilation

The 2025 paper, "Compilation ofQCrank Encoding Algorithm for a Dynamically Programmable Qubit Array Processor" (Balewski et al., 14 Jul 2025), is not the origin of QCrank itself; it is a compilation-and-performance case study that treats QCrank as a practically relevant encoding algorithm and maps it onto a neutral-atom dynamically programmable qubit array. Its principal systems contribution is a hardware-aware implementation strategy, together with a realistic DPQA noise model and comparisons against trapped-ion and superconducting platforms.

That study identifies several DPQA features as particularly relevant to QCrank: large qubit counts, parallel operations, multi-zone architecture, mid-circuit connectivity reconfiguration, and qubit shuttling or coherent atom transport. At the same time, it states clearly that the actual compilation study is restricted to a single-zone architecture, with multi-zone layouts left for future work (Balewski et al., 14 Jul 2025).

The fit between QCrank and DPQAs arises from two structural properties. First, the transpiled circuits exhibit what the paper calls “a high degree of execution parallelism,” including identical single-qubit gates on all qubits and entangling gates applied in parallel layers across several qubits concurrently. Second, the required interactions form a bipartite graph between address and data registers, which is naturally suited to reconfigurable neutral-atom connectivity (Balewski et al., 14 Jul 2025).

The native-gate-transpiled version for neutral atoms uses arbitrary-angle single-qubit rotations, CZ entangling gates, a single global Hadamard layer, sequential $L = n_d \cdot 2^{n_a}.$9 gates with varying angles, and repeated layers of parallel CZ gates. The paper emphasizes two transformations in particular: condensing the Hadamards into a single global Hadamard layer and grouping entangling operations into parallel CZ layers. It states that this transpilation minimizes sequential single-qubit gates while maximizing global operations (Balewski et al., 14 Jul 2025).

For the $2^{n_a}$0 case, which encodes $2^{n_a}$1 real values into $2^{n_a}$2 qubits, the compiler arranges qubits in a rectangular layout. Data qubits are partitioned into rows of size $2^{n_a}$3; when $2^{n_a}$4, these are two rows $2^{n_a}$5 and $2^{n_a}$6. The movement strategy follows three design principles: only move address qubits, use horizontal moves for cyclic permutations among address qubits, and use vertical moves to switch between data rows (Balewski et al., 14 Jul 2025).

The rationale for moving only address qubits is algorithm specific. Under the assumed DPQA noise model, the dominant errors are strongly $2^{n_a}$7-biased for global CZ, CZ-spectator effects, and atom movement. The paper states that $2^{n_a}$8 errors on address qubits propagate through CZ gates to the final measurement and thus do not compromise data encoding quality, whereas $2^{n_a}$9 errors on data qubits can flip $n_d$0 to $n_d$1 and, after the final Hadamard layer, become effectively harmful $n_d$2-type logical effects (Balewski et al., 14 Jul 2025). This asymmetry drives the compilation choice.

The same study identifies a cyclic permutation motif in QCrank. To update address–data pairings between CZ layers, the compiler performs a two-step cyclic shift of the address qubits: first all address qubits move simultaneously left, then only a subset moves in the opposite direction. To reduce vertical movement, CZ gates are applied with one data row, then the address qubits are moved downward row by row; after the last row, the sweep reverses upward. The paper also notes that although a circular layout might seem natural for cyclic permutations, it is incompatible with AOD movement constraints because atom paths would cross (Balewski et al., 14 Jul 2025).

A broader architectural lesson drawn in that work is that maximizing global gate usage emerged as advantageous. This conclusion is specific to the neutral-atom assumptions of the paper and contrasts with settings in which increased parallelism primarily exacerbates crosstalk (Balewski et al., 14 Jul 2025).

5. Role in Monarq and sequence or image transformations

The 2026 paper "Sequence and Image Transformations with Monarq: Quantum Implementations for NISQ Devices" (Balewski et al., 3 Mar 2026) embeds QCrank in a larger encode–compute–decode framework called Monarq by combining QCrank encoding with the EHands protocol for shallow polynomial transformations. In that framework, QCrank is the data-ingestion and structured memory layer, while EHands supplies arithmetic primitives acting only on the data qubits.

The technical reason the two methods compose is that both use the same EVEN expectation-value encoding. QCrank loads many real-valued samples from 1D sequences or serialized 2D grayscale images into data qubits indexed by an address superposition, and EHands consumes those EVEN-encoded qubits directly. The paper identifies this shared encoding as the key reason there is no conversion overhead between loading and computing (Balewski et al., 3 Mar 2026).

Monarq uses the following pipeline: normalize classical data to $n_d$3, use QCrank to load all required sequences or channels into data qubits indexed by address qubits, apply EHands primitives on the data qubits only, and decode either by measuring both address and output qubits for pointwise outputs or by leaving addresses unmeasured to obtain an address-averaged quantity (Balewski et al., 3 Mar 2026). The arithmetic primitives named in the paper are product-with-memory $n_d$4, weighted sum $n_d$5, and negation implemented by an $n_d$6 gate.

Four applications in that paper illustrate QCrank’s functional role.

For pointwise multiplication, described there as the core operation in convolution, QCrank loads two sequences $n_d$7 and $n_d$8 into two data qubits at each address, after which EHands multiplication yields the output $n_d$9. The reported hardware experiment used input size $2^{n_a}$0, $2^{n_a}$1 address qubits, $2^{n_a}$2 total qubits, $2^{n_a}$3 logical CZ gates, $2^{n_a}$4 transpiled two-qubit gates, IBM Pittsburgh, $2^{n_a}$5 shots, a post-processing scaling factor of $2^{n_a}$6, and RMSE $2^{n_a}$7 (Balewski et al., 3 Mar 2026).

For DTFT-style spectral evaluation, QCrank simultaneously loads a signal $2^{n_a}$8 together with trigonometric modulation channels $2^{n_a}$9 and $n_d2^{n_a}$00 for selected probe frequencies. The algorithmically distinctive step is to leave address qubits unmeasured, so the expectation value on an output qubit becomes the average over all addresses. The paper highlights this “in-situ summation” as a way to compute integrals or inner products directly on the QPU. In its gravitational-wave experiment, $n_d2^{n_a}$01 samples implied $n_d2^{n_a}$02, five probe frequencies required $n_d2^{n_a}$03 data channels in total, and the circuit therefore used $n_d2^{n_a}$04 qubits; the experiment was simulated ideally with $n_d2^{n_a}$05 CZ gates and $n_d2^{n_a}$06 million shots per circuit (Balewski et al., 3 Mar 2026).

For squared-gradient computation on images, QCrank stores shifted copies such as $n_d2^{n_a}$07 and $n_d2^{n_a}$08, including duplicates needed for the degree-2 polynomial evaluation. The paper’s $n_d2^{n_a}$09 image experiment tiled the image into $n_d2^{n_a}$10 strips of $n_d2^{n_a}$11 pixels; each circuit used $n_d2^{n_a}$12 address qubits, $n_d2^{n_a}$13 total qubits, $n_d2^{n_a}$14 transpiled CNOT gates, $n_d2^{n_a}$15 shots, the IBM Aachen backend, and calibration factor $n_d2^{n_a}$16. It reports strong visual agreement with classical gradients, especially for significant values $n_d2^{n_a}$17 (Balewski et al., 3 Mar 2026).

For edge detection, QCrank loads eight shifted image channels so that horizontal and vertical squared gradients can be formed and combined. The final threshold is mapped to the sign of an expectation value through a weighted sum with $n_d2^{n_a}$18, yielding a criterion equivalent to $n_d2^{n_a}$19. This was simulated ideally on a $n_d2^{n_a}$20 image tiled into $n_d2^{n_a}$21 tiles of $n_d2^{n_a}$22 pixels, each tile using $n_d2^{n_a}$23 address qubits, $n_d2^{n_a}$24 total qubits, $n_d2^{n_a}$25 CZ gates, and $n_d2^{n_a}$26 million shots (Balewski et al., 3 Mar 2026).

Taken together, these examples show QCrank functioning not merely as a loader of isolated scalar data but as an address-synchronous multichannel representation for stencil-like image operations, modulation banks, and repeated copies required by polynomial transformations. A plausible implication is that QCrank’s utility grows when many aligned channels must be processed pointwise by the same shallow arithmetic circuit.

6. Experimental benchmarks, comparative behavior, and limitations

The 2025 DPQA study evaluates QCrank instances storing $n_d2^{n_a}$27 to $n_d2^{n_a}$28 real numbers in $n_d2^{n_a}$29 to $n_d2^{n_a}$30 qubits and uses RMSE between reconstructed and true data as the main inaccuracy metric (Balewski et al., 14 Jul 2025). For each configuration, the authors generated about $n_d2^{n_a}$31 random sequences in $n_d2^{n_a}$32, executed ideal or noisy simulations, and calibrated the outputs by applying a single global scale factor per configuration to compensate noise-induced dynamic-range shrinkage before computing RMSE. Ideal simulations established a statistical floor at about $n_d2^{n_a}$33, essentially constant across sizes (Balewski et al., 14 Jul 2025).

The same paper compares projected DPQA performance with Quantinuum’s H1-1E emulator and with experiments on IBM Fez. Its summary is that DPQA and H1-1E show comparable expected QCrank accuracy overall, but the relative behavior depends on the ratio $n_d2^{n_a}$34. In the $n_d2^{n_a}$35 case for $n_d2^{n_a}$36 values, H1-1E’s 1D racetrack layout performs better; as $n_d2^{n_a}$37 grows relative to $n_d2^{n_a}$38, H1-1E degrades relative to DPQA, a behavior attributed to limited gate parallelism, limited reconfiguration parallelism, and the 1D architecture (Balewski et al., 14 Jul 2025).

IBM Fez results in that study are worse than the DPQA and H1-1E results because sparse connectivity requires many additional entangling gates for routing. The paper highlights this overhead through the transpiled CZ counts: a logical $n_d2^{n_a}$39-CZ instance became $n_d2^{n_a}$40 CZs on IBM, and a logical $n_d2^{n_a}$41-CZ instance became $n_d2^{n_a}$42 CZs (Balewski et al., 14 Jul 2025). The Monarq paper reports an analogous issue on IBM heavy-hex devices, distinguishing logical CZ counts from substantially larger transpiled two-qubit counts and identifying cumulative two-qubit gate error after transpilation as the main practical limit on hardware (Balewski et al., 3 Mar 2026).

The 2025 study’s DPQA noise model is itself a major contribution. Implemented in Qiskit using parameterized Pauli channels, it includes six sources: local single-qubit gate error, global single-qubit gate error, atom movement error, CZ-spectator error, global CZ error, and measurement or SPAM error. The baseline parameters are specified explicitly as $n_d2^{n_a}$43 for local 1q depolarizing noise, $n_d2^{n_a}$44 for global 1q depolarizing noise, $n_d2^{n_a}$45 for atom-move Pauli probabilities, $n_d2^{n_a}$46 for CZ-spectator Pauli probabilities, $n_d2^{n_a}$47 for $n_d2^{n_a}$48 and $n_d2^{n_a}$49 for the remaining $n_d2^{n_a}$50 two-qubit Pauli terms in the global CZ channel, and $n_d2^{n_a}$51 for measurement noise (Balewski et al., 14 Jul 2025). The authors also scale all baseline parameters by $n_d2^{n_a}$52 to form a likely performance band.

Several limitations recur across the papers. The 2023 paper emphasizes readout cost, analog precision limits, noise sensitivity in UCR decompositions, and backend dependence between trapped-ion and transmon implementations (Balewski et al., 2023). The 2025 compilation study notes that its DPQA analysis assumes a single-zone architecture, omits leakage, atom loss, and explicit transport-time-induced infidelity, and does not include decoherence accumulation from elapsed time because $n_d2^{n_a}$53 s are assumed while transport times are only $n_d2^{n_a}$54–$n_d2^{n_a}$55 (Balewski et al., 14 Jul 2025). The 2026 Monarq paper identifies large shot requirements, gate-infidelity accumulation, circuit-size limits, the need for tiling on larger images, scaling costs with polynomial degree, and empirical attenuation correction on hardware (Balewski et al., 3 Mar 2026).

QCrank is also situated relative to QBArt in the original paper. QCrank is the angle-based, address-conditioned encoding using uniformly controlled rotations, while QBArt is presented as a distinct representation with a different balance between arithmetic convenience and measurement overhead (Balewski et al., 2023). The original paper associates QCrank with compact analog loading of real-valued data and QBArt with a more bit- or arithmetic-oriented representation.

Across these studies, QCrank emerges as a structured encoding primitive rather than a standalone algorithmic speedup claim. It offers compact representation, address-synchronous parallelism, and a regular circuit architecture, but its practical value is conditioned by shot complexity, transpilation overhead, and hardware-specific error structure. This suggests that the significance of QCrank lies less in bypassing classical I/O costs than in enabling coherent, multichannel, address-indexed processing pipelines on near-term quantum hardware (Balewski et al., 2023, Balewski et al., 14 Jul 2025, Balewski et al., 3 Mar 2026).