On-Chip Integration of 2D Materials

• On-Chip Integration of 2D Materials is defined by using atomically thin layers like graphene and TMDs to enhance photonic, electronic, and quantum device functionalities through van der Waals adhesion.
• Integration approaches employ diverse methods such as CVD, dry-transfer, and 2D printing to achieve sub-micron alignment and scalable, wafer-level manufacturing.
• These techniques yield devices with enhanced light–matter interactions, high carrier mobilities, and efficient optical coupling, advancing on-chip light sources, modulators, and quantum systems.

Two-dimensional (2D) materials, comprising atomically thin layers such as graphene, transition-metal dichalcogenides (TMDs), and hexagonal boron nitride (hBN), have emerged as crucial building blocks for next-generation on-chip photonics and electronics. Their unique, substrate-agnostic van der Waals adhesion, diverse optical and electronic properties, and compatibility with a wide array of material platforms have enabled diverse integration strategies into photonic, optoelectronic, quantum, and meta-devices with scaling potential toward wafer-scale manufacturing. This article presents a comprehensive account of the principles, methodologies, device architectures, and integration challenges for the on-chip deployment of 2D materials, referencing canonical and recent developments across the photonics, electronics, and quantum domains.

1. Principles and Advantages of 2D Materials in On-Chip Integration

2D materials exhibit atomic-scale thickness, high crystal quality with no dangling bonds, wide bandgap tunability (from zero in graphene to ∼6 eV in hBN), broadband optical absorption (2.3% per graphene monolayer, >10% in monolayer TMDs), strong nonlinear optical susceptibility (e.g., χ² up to 800 pm/V in 3R-MoS₂), and high carrier mobilities (up to 10⁵ cm²/V·s). Their atomically sharp interfaces and van der Waals surfaces permit integration onto arbitrary substrates—silicon, metals, dielectrics—without concern for lattice mismatch or thermal strains that limit epitaxial approaches.

Key advantages for integrated on-chip systems include:

• Universal adhesion via van der Waals forces, enabling “plug-and-play” transfer onto photonic and electronic platforms without strict substrate requirements (Frydendahl et al., 26 Mar 2025, Frydendahl et al., 11 Jun 2025).
• Strong light–matter interaction and high exciton binding energy, supporting efficient emission, detection, electro-optic modulation, and nonlinear processes at the few-nm device scale (Liu et al., 2018, Sarkar, 15 May 2025).
• Broad functional diversity—2D materials function as conductors, semiconductors, insulators, and correlated quantum phases (e.g., topological insulators, superconductors) on chip (Jia et al., 2024).
• Compatibility with CMOS back-end-of-line (BEOL) due to low-temperature transfer and growth methods (Moss, 2022, Lemme et al., 2021).
• Deterministic patterning and heterostructuring, allowing for engineered quantum states, enhanced light extraction, and reconfigurable device operation (Azzam et al., 2021, Tang et al., 2023).

2. Fabrication Methods and Integration Workflow

Integration of 2D materials into chip-scale devices exploits a hierarchy of fabrication techniques, which include both top-down (patterning and transfer) and bottom-up (direct growth) strategies (Moss, 2022, Moss, 15 Apr 2025):

• Material Synthesis: Mechanical exfoliation delivers the highest material quality but suffers from small lateral dimensions (<100 μm) and low throughput. Chemical vapor deposition (CVD) and molecular beam epitaxy (MBE) enable wafer-scale monolayer and heterostructure growth (defect density ∼10¹⁰ cm⁻²), albeit at higher temperatures (650–1000 °C) (Moss, 2022, Lemme et al., 2021).
  • Wafer bonding and transfer processes have matured for PtSe₂, MoS₂, and WS₂, with BEOL-compatible synthesis below 400 °C for some 2D systems (Lemme et al., 2021, Moss, 15 Apr 2025).
• Transfer Techniques: These are typically categorized as dry-transfer (PDMS or PPC/PDMS stamping, sub-micron alignment), wet-transfer (PMMA-mediated, >90% yield but subject to polymer residues), and hybrid methods (semi-dry, inkjet printing, or self-assembly). The emergence of "2D material printers" (lithography + pin-press) has enabled sub-micron deterministic placement with minimal cross-contamination, supporting integration onto pre-taped-out photonic chips (Ma et al., 2017, Moss, 2022).
• On-Chip Patterning: Photolithography, electron-beam lithography, nanoimprint, and laser direct-writing yield device features down to tens of nanometers. Selective etching and lift-off steps define contacts and active regions. Device-resolved alignment between waveguides and exfoliated or CVD-grown flakes is typically sub-micron (±0.5–2 μm) (Maiti et al., 2018, Moss, 15 Apr 2025).
• Heterostructure Stacking and Encapsulation: Layer-by-layer stacking of 2D crystals—hBN, TMDs, graphene—realized by dry pick-up with PPC/PDMS, enables vertical and lateral heterojunction construction and precise twist-angle control for moiré-engineered devices (Moss, 2022, Tang et al., 2023). Encapsulation with hBN, Al₂O₃, or parylene passivates air-sensitive materials (e.g., black phosphorus) and stabilizes optoelectronic characteristics (Moss, 15 Apr 2025, Khelifa et al., 2022).
• Specialized Techniques: Nano-subsidence employs capillary and van der Waals pressures to conformally integrate 2D layers onto structured 3D substrates, yielding high-yield, uniform contact (∼1 μm alignment, >94% device survival) (Li et al., 2023). Chalcogenide glass-on-graphene deposition offers a monolithic, low-temperature route to integrate, passivate, and gate 2D layers, supporting complex multilayer photonic circuit geometries (Lin et al., 2017).

3. Device Architectures and Integrated Photonic Functions

2D materials enable a broad spectrum of photonic device architectures and functions, spanning active and passive roles:

• On-Chip Light Sources: Monolayer TMDs (MoSe₂, WSe₂) serve as on-chip light emitters in both plasmonic and dielectric waveguides. Dry visco-elastic or PC-assisted transfer methods enable robust coupling of 2D photoluminescence into plasmonic slot waveguides and nanoantenna couplers with injection efficiency up to ∼20% (Frydendahl et al., 26 Mar 2025, Frydendahl et al., 11 Jun 2025). Electrically driven light-emitting diodes (LEDs) fabricated from van der Waals (vdW) heterostructures (e.g., WSe₂ as emitter, hBN as tunnel barrier, Gr as contacts) have been patterned into fully integrated waveguide geometries, achieving external quantum efficiencies of ∼4% and sub-0.2 dB/μm propagation losses in h-BN platforms (Khelifa et al., 2022).
• Single-Photon and Quantum Light Sources: Quantum emitters in 2D hosts (hBN, WSe₂) have been directly coupled to tapered fibers (10% measured fiber coupling efficiency, limited by dipole alignment and position) (Schell et al., 2017), to silicon-nitride (SiN) waveguides (∼7% FDTD-extracted coupling), and to microcavities for Purcell-enhanced emission and improved indistinguishability (Peyskens et al., 2019). Site-controlled placement by strain engineering, STEM/e-beam patterning, and deterministic transfer allows for scalable integration of SPE arrays with photonic circuits (Azzam et al., 2021).
• Entangled Photon Pair Sources and Nonlinear Optics: 2D vdW materials with high χ² (3R-MoS₂, r-BN, NbOCl₂) facilitate efficient on-chip generation of entangled photon pairs via spontaneous parametric down-conversion (SPDC), with demonstrated brightness up to 8,667 Hz/(mW·mm), fidelities exceeding 0.93, and concurrence up to 0.973 (Sarkar, 15 May 2025). Phase matching requirements are mitigated via dispersion engineering and cavity-resonator architectures. MEMS-actuated platforms enable in situ twist and interlayer tuning for real-time control of nonlinear susceptibility, paving the way for dynamically reconfigurable quantum sources (Tang et al., 2023).
• Modulators and Switches: Graphene and semiconducting TMDs support high-efficiency, submicron electro-optic modulators via Pauli-blocking and refractive index tuning, capable of achieving energy-per-bit down to the attojoule regime and modulation bandwidths projected beyond 100 GHz (Ma et al., 2017). Integration strategies—plasmonic slot, ring resonator, or photonic crystal—tailor the optical mode overlap and confinement factor, crucial for maximizing modulation efficiency given the atomic-scale thickness of the active layer (Moss, 15 Apr 2025).
• Infrared Photodetectors: Waveguide-integrated, cavity-enhanced, and plasmon-enhanced 2D detectors (graphene, BP, TMDs) exhibit responsivities from 0.1 to >10 A/W, specific detectivity D* up to 10¹⁵ Jones, and operation bandwidths >20 GHz. Device architectures incorporate Si, SiN, or chalcogenide glass waveguides, with design emphasis on maximizing optical overlap and minimizing contact resistance (Liu et al., 2018, Lin et al., 2017).
• Heterogeneous Integration with MEMS and 3D Architectures: Recent work demonstrates on-chip MEMS platforms for multi-degree-of-freedom control (twist, pressure, separation) of 2D nanostructures, enabling dynamic reconfiguration of nonlinear optical response, generation of topological singularities (merons), and tuning of quantum entanglement properties (Tang et al., 2023). Nano-subsidence and hybrid 2D/Si architectures further extend integration to non-planar substrates and complex system-on-chip layouts (Li et al., 2023).

4. Performance Metrics and Theoretical Formalism

On-chip 2D material devices are evaluated on figures of merit directly linked to integration geometry, material quality, and mode engineering:

• Coupling Efficiency (η, β): For dipole emitters coupled to fibers/waveguides, η is determined by the overlap integral of the emitter near-field and the guided mode, with measured values ranging from ∼7% for waveguide-coupled SPEs in SiN to ∼10% for fiber-coupled hBN SPEs (Peyskens et al., 2019, Schell et al., 2017).
• Purcell Factor (F_P): Spontaneous emission enhancement, critical for improving SPE brightness and reducing lifetime, is given by $F_P = (3/4\pi^2)\cdot(\lambda/n)^3\cdot(Q/V)$, with F_P exceeding 100 demonstrated in photonic crystal cavities (Azzam et al., 2021).
• Electro-optic Modulation Figures: The energy-per-bit $E_\mathrm{Elec} \propto \mathrm{Volume}$ and modulation bandwidth $f_{3dB}$ are optimized by reducing device volume and capacitance, employing strong index tunability even at ultralow mode overlap (Γ), characteristic of monolayer integration (Ma et al., 2017).
• Photodetector Responsivity and Bandwidth: On-chip photodetectors with waveguide or plasmonic coupling have achieved responsivity R>0.1 A/W, D*≥10¹² Jones, and electronic bandwidths from tens of MHz to >20 GHz (Liu et al., 2018, Khelifa et al., 2022).
• Integration Yield and Alignment Accuracy: Existing pilot-line processes report >90% device yield on 4" wafers using CVD growth and photolithography, with alignment precision down to ±0.5 μm using deterministic transfer or “2D printer” methods (Moss, 2022, Ma et al., 2017).

5. Integration Challenges, Scalability, and Solutions

Major bottlenecks hindering industrial-scale deployment of on-chip 2D materials include (Moss, 15 Apr 2025, Lemme et al., 2021, Moss, 2022):

• Residue and Contamination: Polymer and organic contamination from transfer processes degrade interfaces, mobility, and optical loss. Dry-transfer, polymer-free pick-up, and direct-evaporation techniques address this.
• Thermal and Environmental Stability: Many 2D materials (BP, MoTe₂) are sensitive to air and moisture; encapsulation with hBN, Al₂O₃, or glass prolongs operational lifetime (>80 days for BP with 6 nm Al₂O₃) (Moss, 15 Apr 2025).
• Alignment, Patterning, and Wafer-Level Uniformity: Achieving sub-micron alignment is critical for high β and device reproducibility; robotics and in-line metrology (Raman, AFM, SEM) are being developed for real-time monitoring (Moss, 15 Apr 2025).
• Scalability and Standardization: Large-area CVD, roll-to-roll transfer, and bonding processes are actively being standardized (IEC, ISO) to match CMOS requirements (defect density <10¹⁰ cm⁻², contact resistivity <100 Ω·µm) (Lemme et al., 2021, Moss, 15 Apr 2025).
• CMOS Compatibility: Growth and transfer temperatures must remain <400 °C to avoid contamination and preserve BEOL process flows. Integration of 2D/Si and 2D/III–V hybrid platforms is enabled by van der Waals assembly and compatible etching/passivation (Moss, 2022).

6. Advanced Integration Paradigms and Future Directions

Recent progress has demonstrated the full spectrum of on-chip device concepts encompassing quantum photonics, nonlinear optics, optoelectronics, and hybrid architectures:

• Hybrid Plasmonic–Dielectric and Multimodal PICs: 2D materials interfaced with plasmonic slot-waveguides on gold, Si, and SiN realize deep sub-wavelength confinement and enable universal emitter and detector integration across varied PIC substrates (Frydendahl et al., 11 Jun 2025, Frydendahl et al., 26 Mar 2025).
• Reconfigurable and MEMS-Actuated Devices: On-chip MEMS platforms offer dynamic control of heterostructure twist, pressure, and separation, facilitating real-time tunability of nonlinear and quantum properties, and access to synthetic topological dimensions (Tang et al., 2023).
• Scalable Photonic Quantum Circuits: Arrays of site-engineered SPEs, on-chip multiplexed EPP sources, and monolithic integration of sources, modulators, detectors, and routing meshes are under development for fully quantum-enabled PICs (Sarkar, 15 May 2025, Azzam et al., 2021).
• Manufacturing Roadmap: Continued adoption of automated, in-line metrology; large-area, low-defect CVD; and reliable transfer/bonding standards is expected to bridge the manufacturing readiness gap between laboratory prototypes and industrial-scale 2D-material–enabled photonic systems (Moss, 15 Apr 2025, Lemme et al., 2021).

7. Summary Table: Principal Integration Methods

Integration Method	Throughput	Alignment Precision	Typical Application Domains
CVD Direct Growth	High	Moderate (μm)	Wafer-scale films, electronics, photonics
Dry Transfer (Stamping)	Low/Medium	Sub-μm	Deterministic single-device loading
Wet Transfer (PMMA)	Medium	10 μm	Large-area coverage, increased contamination
2D Printer (Pin-Press)	Low/Medium	~500 nm	Selective, device-resolved photonic chips
Wafer Bonding	High	<1 μm (with planarization)	Batch process, pilot lines
Inkjet/Solution Printing	Medium	10–50 μm	Maskless, additive, sensor arrays

The field continues to develop, with multiple paths toward efficient, scalable, and functional integration of 2D materials on chip, enabling a new era of hybrid photonic, electronic, and quantum technologies (Moss, 2022, Moss, 15 Apr 2025).