Thermal Scanning-Probe Lithography (tSPL)

• Thermal scanning-probe lithography (tSPL) is a nanofabrication technique where a resistively heated AFM tip removes material from a thermally sensitive film, achieving sub-10 nm resolution.
• The method leverages confined thermal interactions and closed-loop topographic readout to produce precise grayscale relief patterns with minimal line-edge roughness.
• tSPL integrates advanced resist stack engineering and versatile transfer routes across materials like silicon and 2D semiconductors, with scaling potential via parallel cantilever arrays.

Thermal scanning-probe lithography (tSPL) is the heat-driven branch of scanning probe lithography in which a nanometer-sharp, resistively heated AFM tip writes patterns directly into a thermally responsive film, most commonly by local material removal that produces topographic relief. In the standard implementation, a silicon tip on a heated cantilever locally decomposes or sublimates a thermally labile resist such as polyphthalaldehyde (PPA), and the same instrument can often image the surface before, during, and after writing. Across the literature, tSPL is defined by strong thermal localization at the tip-sample junction, maskless direct writing under ambient conditions, sub-10 nm lateral capability, grayscale depth control, and frequent integration with closed-loop topographic readout and downstream transfer into silicon, metals, van der Waals materials, and other functional substrates (Garcia et al., 2015).

1. Fundamental operating principle

tSPL relies on the confinement of heat to the tip-sample contact. In the review framework of advanced scanning probe lithography, it is distinguished from thermochemical SPL (tc-SPL): in tSPL the heated probe mainly causes material removal to form topographic relief, whereas in tc-SPL the local heating is used to trigger a chemical transformation that changes composition or functionality. The relevant thermal interaction area is of order a few nm$^2$, set by the tip apex, and the actual surface temperature is determined by the thermal resistance of the substrate and the combined thermal resistance of the tip and the tip-sample interface rather than by the heater temperature alone. For sharp tips with radii around 5 nm contacting polymer films thicker than the contact size, the polymer surface temperature can be reduced by about a factor of two relative to the heater temperature. Silicon heater cantilevers typically sustain roughly $800$–$1000^\circ\text{C}$, with thermal time constants of $5$ to $>100\,\mu\text{s}$ (Garcia et al., 2015).

The process window is therefore governed by the coupled effects of heater temperature, contact force, dwell time, and scan speed. In polymer-based tSPL, the heated tip is brought into contact or near-contact with a thermally sensitive film, and local depolymerization, sublimation, or ablation creates a depth-modulated pattern. PPA is especially effective because cleavage of a single bond initiates self-amplified depolymerization, making the response highly sensitive and fast. This underlies the use of tSPL not only for binary openings but also for three-dimensional grayscale relief structures written with single-nanometer absolute depth precision (Garcia et al., 2015).

A recurring operational feature is combined write/read functionality. In one high-resolution implementation, the tip writes in the trace direction and reads back in retrace, so the thermal probe is simultaneously a patterning tool and a metrology instrument. This combined mode enables direct comparison between intended and realized topography and supports closed-loop lithography rather than open-loop exposure alone (Wolf et al., 2014).

2. Resist systems, stack engineering, and transfer routes

The most developed tSPL workflows use engineered multilayer stacks in which the probe writes only a shallow thermal image in the top resist and a subsequent transfer sequence amplifies that image into a much thicker functional mask or directly into the target material. A representative stack for silicon patterning consists of a $\sim 9$ nm PPA imaging layer, an evaporated SiO$_2$ hardmask only $2$–$3$ nm thick, and a 50 nm polymeric transfer layer such as HM8006. The probe writes shallow trenches typically $4$–$800$0 nm deep in PPA; an $800$1 plasma thins the remaining PPA in unwritten regions to about 3 nm; a CHF$800$2 RIE step transfers the image into the ultrathin oxide; and the oxide then acts as a durable mask that amplifies the pattern vertically into the transfer layer because SiO$800$3 etches much more slowly than the polymer in oxygen plasma. The transfer layer finally serves as the etch mask for silicon in $800$4 deep reactive ion etching. The same three-layer concept can be adapted to metal lift-off by replacing HM8006 with 53 nm PMMA and using solvent removal after deposition (Wolf et al., 2014).

In that process architecture, the ultrathin oxide is the critical amplifier. Reducing the SiO$800$5 hardmask from an earlier 4 nm implementation to $800$6–$800$7 nm was identified as essential for preserving shallow tSPL-written features while maintaining sufficient robustness for transfer. Under the reported CHF$800$8 conditions, the SiO$800$9:PPA etch selectivity is about $1000^\circ\text{C}$0, so the oxide pattern corresponds to an effective transferred depth of less than 1.5 nm in PPA terms. Combined with a measured PPA roughness of about 2 nm, this implies that a minimum written depth of roughly $1000^\circ\text{C}$1–$1000^\circ\text{C}$2 nm is needed for reliable transfer. The same study notes that a 2 nm oxide membrane can support more than 90 nm transfer into HM8006 and more than 150 nm into PMMA for the tested etch conditions (Wolf et al., 2014).

Other implementations emphasize different transfer logic. For additive fabrication of few-layer MoS$1000^\circ\text{C}$3 nanocircuits, tSPL writes a high-resolution sacrificial polymer mask rather than directly modifying the TMD. A bilayer of PMMA/MA ($1000^\circ\text{C}$4 nm) and PPA ($1000^\circ\text{C}$5 nm) is patterned, chemically developed to expose selected substrate regions, and then used as a negative-profile mask for subsequent MoS$1000^\circ\text{C}$6 deposition and lift-off. This converts a continuous growth-and-lift-off process into arbitrarily positioned nanoscale semiconductor circuits on wafer-scale substrates (Giordano et al., 2022). In a photonic route to perforated silver films, the stack is silica substrate / Ag (30 nm) / PMMA/MA (30 nm) / PPA (20 nm); the tSPL step opens the PPA, ethyl alcohol selectively removes the exposed PMMA/MA, and aqueous Fe(NO$1000^\circ\text{C}$7)$1000^\circ\text{C}$8 etches the exposed Ag, yielding a perforated metallic film without a special negative-tone resist (Pellegrini et al., 14 Oct 2025).

Not all tSPL processes are resist-transfer workflows. In a superconducting implementation, an ultrasharp heated Si tip directly scribes across pre-patterned YBa$1000^\circ\text{C}$9Cu$5$0O$5$1 microbridges, forming a narrow constriction that acts as a Josephson-like weak link. That result shows that, in some material systems, the thermal probe can function as a direct thermomechanical trimming tool rather than solely as a resist writer (Duong et al., 2024).

3. Resolution, fidelity, and quantitative metrology

The most direct definition of a patterning process resolution is the smallest half-pitch feature that can be transferred onto the substrate. Using the three-layer PPA/SiO$5$2/HM8006 process, dense silicon lines were written at a half pitch of 18.3 nm, initially $5$3–$5$4 nm deep in a 9.3 nm PPA film, and then etched into silicon to approximately 65 nm depth. Comparison structures at 22.9 nm and 27.5 nm half pitch were also reported. Line-edge roughness was defined as

$5$5

with $5$6 values of $5$7 nm, $5$8 nm, and $5$9 nm for half pitches of 18.3, 22.9, and 27.5 nm, respectively; the highest-resolution structures were summarized as having less than 3 nm LER in both the transfer layer and silicon (Wolf et al., 2014).

At the level of general capability, the review literature reports $>100\,\mu\text{s}$0 nm resolution, half-pitch down to 10 nm without proximity corrections, field stitching at $>100\,\mu\text{s}$1 nm precision, and throughput of approximately $>100\,\mu\text{s}$2–$>100\,\mu\text{s}$3, with a representative example of 880 × 880 pixels written in 12.8 s. The same review identifies parallel cantilever arrays as the main route toward larger-area manufacturing, with projected throughputs above $>100\,\mu\text{s}$4 (Garcia et al., 2015).

Quantitative fidelity analysis has become increasingly formalized. In the workflow for smooth topographic landscapes, tSPL and AFM datasets are corrected for artefacts, fit to analytical functions, and compared within the open-source software package FunFit. The software imports NanoFrazor .top and NanoScope .spm data, applies median-based line correction and plane leveling, fits preset or user-defined functions by nonlinear least squares, and outputs fit parameters, residuals, FFT plots, and RMSE as a fidelity metric. In a graphene/hBN heterostructure application, a sinusoidal landscape written into PPA and transferred into hBN was analyzed in this way, yielding a measured wavelength of 296 nm, a modulation depth of 12 nm after transfer, an RMSE of 1.3 nm in the PPA before etch transfer, and 1.4 nm in hBN afterward (Sørensen et al., 2024, Lassaline et al., 11 Aug 2025).

In metallic perforation, fidelity can be assessed directly against the intended photonic geometry. Cross-shaped unit cells designed with length 2.5 $>100\,\mu\text{s}$5m and width 645 nm were measured after transfer with average dimensions of 2.48 $>100\,\mu\text{s}$6m and 638 nm, corresponding to sub-10 nm pattern transfer fidelity relative to the target design. The same study also reports a failure case in which oxidation-induced topographic nonuniformity led to only 12 nm pattern depth instead of the required 20 nm PPA opening, preventing proper perforation (Pellegrini et al., 14 Oct 2025).

4. Grayscale relief, mathematical landscapes, and closed-loop optimization

A distinctive capability of tSPL is grayscale topographic patterning: the probe can sculpt continuously varying height profiles rather than only binary trenches or holes. In the smooth-landscape protocol, a silicon tip mounted on a heated cantilever is brought into contact with PPA and locally decomposes or sublimates the resist. Because tip position, temperature, force, and scan path are controllable, the process produces mathematically defined contours at nanometer precision and, crucially, does so with the same tool that measures the evolving profile. The study emphasizes periodic and quasiperiodic landscapes, including a sinusoidal landscape and a quasicrystal-like landscape implemented as a superposition of cosines with rotational symmetry (Sørensen et al., 2024).

The analytical fitting formalism is explicit. For a sinusoidal landscape, the fitted form is

$>100\,\mu\text{s}$7

For a quasiperiodic landscape, the fitted form is

$>100\,\mu\text{s}$8

with $>100\,\mu\text{s}$9 in the quasicrystal example. These fits provide a basis for parameter extraction, residual analysis, and FFT comparison between target and fabricated topographies (Sørensen et al., 2024).

This grayscale capability has been extended from resist topography to functional electronic landscapes. In van der Waals heterostructures, tSPL was used to pattern a sinusoidal relief in a 75 nm PPA layer and transfer it by $\sim 9$0 RIE into the top hBN dielectric of an encapsulated graphene device. The thickness modulation was described as

$\sim 9$1

with a period of about 300 nm. After transfer, electrostatic gating through the modulated dielectric imposed a spatially varying top-gate capacitance and hence a spatially varying carrier density, producing resistance-peak spreading and low-field commensurability oscillations in transport. This use of tSPL turns vertical thickness control into a programmable electrostatic texture without directly patterning the graphene itself (Lassaline et al., 11 Aug 2025).

A plausible implication is that tSPL’s defining advantage is not merely small feature size but the coupling of direct-write grayscale fabrication to in situ quantitative readout. In the 2024 landscape study, the practical workflow is explicitly iterative: design a mathematical landscape, convert it to a bitmap, write in PPA, measure, fit in FunFit, compare fitted parameters and residuals to the target, adjust writing conditions or etch parameters, and repeat until transfer fidelity is optimized (Sørensen et al., 2024).

5. Device integration across materials systems

tSPL has been integrated into silicon nanofabrication, metal lift-off, buried-object overlay, 2D semiconductor processing, strain engineering, superconducting weak-link fabrication, and photonic metasurface patterning. In silicon, the three-layer transfer process produced sub-20 nm half-pitch structures etched to approximately 65 nm depth with LER below 3 nm. In metal lift-off, the same basic architecture enabled complex high-resolution nickel features with sub-30 nm arm widths and an apex opening of about 10 nm; a device demonstration produced 50 nm half-pitch dense nickel contacts to an InAs nanowire (Wolf et al., 2014).

One of the clearest demonstrations of tSPL as an overlay technology is markerless nanowire contacting. In the nickel/InAs device, the nanowire and existing e-beam-defined features were topographically sensed by the tSPL tool and the electrode pattern was written in registry to the measured surface, using a 14 nm write pixel size and a nominal wire width of 28 nm. A related buried-feature study formalized this capability by showing that, for sub-micron buried structures, the dry-film surface topography is a centered Gaussian-blurred replica of the underlying object rather than an upstream-shifted shadow. For an InAs nanowire of diameter 27 nm buried under a 61 nm PMMA film, the surface signature amplitude was about 2.9 nm, and the subsequent tSPL-defined contact placement achieved a measured overlay error of 2.9 nm perpendicular to the wire axis (Rawlings et al., 2017).

In 2D semiconductors, tSPL has been used in both additive and grayscale-strain modes. For wafer-scale few-layer MoS$\sim 9$2, the technique defines sacrificial polymer masks that guide subsequent growth and lift-off, producing nanopaths, nanofingers, and nanostripes with widths below 200 nm while preserving the semiconducting 2H phase. Raman spectroscopy showed the characteristic $\sim 9$3 and $\sim 9$4 modes at 383 and 408 cm$\sim 9$5, KPFM measured a MoS$\sim 9$6-to-SiO$\sim 9$7 CPD contrast of about 200 mV and an estimated work function of about 5.25 eV, and conductive AFM found a local current decay approximately obeying $\sim 9$8, with an estimated resistivity of about $\sim 9$9 under a long-channel approximation (Giordano et al., 2022). In a different 2D-material workflow, grayscale tSPL patterned deterministic faceted nanoridges in $_2$0 nm PPA on glass/ITO, with 530 nm pitch, $_2$1 nm height, $_2$2 nm lateral resolution, and $_2$3 nm depth resolution. Conformal transfer of mono- and few-layer MoS$_2$4 onto these asymmetric facets generated directional tensile strain, and KPFM showed asymmetric CPD dips of about 130 mV for monolayer and 150 mV for few-layer MoS$_2$5, followed by asymmetric Au–MoS$_2$6 lateral heterojunction behavior after glancing-angle Au evaporation (Zambito et al., 29 May 2025).

tSPL has also been extended to material systems outside polymer-mask transfer. In YBCO, a commercial NanoFrazor system with a heated Si tip of radius $_2$7 nm directly trimmed 2 $_2$8m-wide superconducting microbridges into weak links of width about 200 nm and length $_2$9 nm, using $2$0, pixel step 2 nm, contact time 40 $2$1s, and scan speed $2$2. The trimming reduced the critical current from 4.9–5.4 mA to about 0.3 mA, produced a Fraunhofer-like magnetic diffraction pattern with periodicity about 27 mT, and yielded microwave-response signatures consistent with SNS or SS’S-type Josephson junction behavior (Duong et al., 2024). In nanophotonics, tSPL defined openings in PPA on Ag films that were subsequently transferred by alcohol development of PMMA/MA and Fe(NO$2$3)$2$4 wet etching, producing perforated silver films for cross-shaped IR-filter unit cells (Pellegrini et al., 14 Oct 2025).

6. Misconceptions, limitations, and scaling directions

A recurrent misconception is that tSPL is simply a heated version of conventional AFM scratching. The literature instead presents it as a thermally localized nanolithography platform with integrated metrology, in which material response is governed by confined heat flow, force control, and reaction or decomposition kinetics rather than by purely mechanical ploughing. A second misconception is the conflation of tSPL with tc-SPL: the former is principally topographic material removal, whereas the latter uses local heating for chemical conversion (Garcia et al., 2015). A third misconception, important for overlay fabrication, is the assumption that nanoscale buried features under spin-coated films are inevitably shifted laterally by spin-coating flow. For sub-micron features, the Gaussian-convolution model and the 2.9 nm overlay demonstration contradict that “upstream shift” paradigm (Rawlings et al., 2017).

The principal limitation remains throughput. tSPL is a serial writing method, and although its throughput is unusually high for a probe-based approach, practical deployment beyond prototyping requires either restricted-area patterning or parallelization. Tip lifetime and tip geometry are also critical because the entire process depends on a sharp, thermally stable apex whose shape does not drift during writing. Thermal spread into the substrate constrains the process window, and high spatial resolution therefore favors materials with sharply defined thermal response, notably PPA and related thermally labile films (Garcia et al., 2015).

Process robustness is strongly material- and recipe-dependent. The quantitative landscape protocol notes that datasets must be sampled well, patterned and flat reference regions are both required, transfer fidelity depends on careful calibration of writing temperature, force, and etch rate, and etch-induced roughness can make fitting difficult. The reported hBN transfer rate of about 1.35 nm/s for both PPA and hBN is explicitly described as recipe- and tool-dependent (Sørensen et al., 2024). In metallic perforation, Ag oxidation caused uneven topography, blurred features, varied etch depth in the PPA, and outright failure of a unit cell whose tSPL depth reached only 12 nm instead of the required 20 nm (Pellegrini et al., 14 Oct 2025).

The longer-term scaling direction identified in the review literature is parallel cantilever technology. Arrays up to $2$5 cantilevers have been fabricated, and even linear arrays of 30 thermal cantilevers in a commercial AFM were described as capable of writing and reading more than 1 million pixels per second, potentially patterning areas of about $2$6 per action. This suggests that the central challenge for tSPL is no longer whether nanoscale, grayscale, closed-loop thermal patterning is feasible, but how serial direct writing is translated into scalable manufacturing without losing the depth precision, overlay accuracy, and material versatility that distinguish the method (Garcia et al., 2015).