Etch-Back Assisted CMP for 3D Photonics

• E-CMP is a planarization technique that integrates a pre-polish etch-back to collapse step heights, ensuring nanometer-scale smoothness for 3D photonic circuits.
• It decouples flattening from smoothing by first using an isorate ICP dry etch to nearly eliminate oxide topography, followed by a brief CMP to restore planarity.
• The method yields exceptional spacer uniformity and low vertical transition loss, enabling robust inter-layer couplers and high-Q optical cavities.

Etch-Back Assisted Chemical Mechanical Polishing (E-CMP) is a planarization methodology for wafer-scale three-dimensional photonic integrated circuits in which a lithography/etch “step-height reduction” stage is inserted immediately before a short, gentle chemical mechanical polishing step. In the reported dual-layer silicon nitride (SiN) platform, E-CMP is used to planarize the intermediate silicon dioxide (SiO$_2$) spacer whose thickness directly sets inter-layer coupling strength and therefore the transition loss of vertical tapers. The method separates “flattening” from “smoothing”: an isorate dry etch collapses most of the oxide topography, and a brief CMP then restores nanometer-scale smoothness and global planarity. In the demonstrated 4-inch wafer process, this yielded a bottom-to-bottom (B-B) distance mean of 872 nm with a coefficient of variation of 2.06%, typical inter-layer transition loss as low as 6 mdB, and single-layer propagation losses of 0.077 and 0.068 dB/cm on the two SiN waveguide layers (Huang et al., 14 Apr 2026).

1. Concept and distinguishing features

E-CMP augments conventional CMP with a pre-polish etch-back that specifically targets step-height collapse. After lower-layer patterning and oxide deposition, the spacer surface contains topography with steps of approximately 400 nm originating from buried SiN features. In E-CMP, this step landscape is conformally coated with a nanoimprint lithography resist, and an ICP dry etch is tuned so that the resist and SiO$_2$ etch at the same rate, with effective selectivity of approximately $1{:}1$. The resist’s conformal cap is thereby transferred into the oxide, reducing a 400 nm step to 20–25 nm residual relief, corresponding to approximately 94% reduction. A short CMP then removes the remaining relief and polishes the spacer to RMS roughness of approximately 0.2 nm (Huang et al., 14 Apr 2026).

The method differs from conventional single-pass CMP in both objective and failure mode. Conventional CMP must remove the full topography burden, so removal rate and planarity depend strongly on local step height, pattern density, and die-edge pressure or velocity fields. The characteristic failure modes are dishing, erosion, edge roll-off, and wafer-to-wafer variability when long polish times are required. In the demonstrated 3D photonic integrated circuits, CMP-only wafers exhibited nonuniform white-light interference patterns consistent with large spacer thickness variations. E-CMP reduces those effects by making CMP a finishing step rather than the primary leveling mechanism.

E-CMP is also distinct from other planarization strategies that appear superficially similar. Damascene CMP can deliver excellent surface planarity for high-confinement SiN, but requires complex multi-mask trench-fill flows, backside film removal, or nonstandard thick substrates to control stress and bow, and its complexity scales poorly with layer count. Spin-on-glass planarization offers excellent local gap fill, but residual shrinkage, trapped porosity, and modulus mismatch can degrade optical loss and are difficult to control uniformly at wafer scale; subsequent etch-back or CMP is often still required. Pure dry etch-back is effective for blanket thinning but does not by itself provide true global planarity or nanometer-level smoothness. A recurrent misconception is therefore that E-CMP is merely a shortened CMP or merely a dry etch-back; in the reported process, its defining feature is the explicit separation of topography collapse from final smoothing (Huang et al., 14 Apr 2026).

2. Process stack and fabrication sequence

The demonstrated platform is a dual-layer SiN-on-Si stack built on a standard 4-inch silicon wafer. The lower cladding is 4 $\mu$m thermal/dry-wet SiO$_2$. Layer 1 is a PECVD SiN core designed to be 400 nm thick; 470 nm is deposited at $360^\circ$C using alternating 13.56 MHz / 100 kHz plasma to compensate for densification, with average intrinsic film stress of 51.18 MPa, and the post-anneal thickness is approximately 400 nm after a $1150^\circ$C, 2 h, N$_2$ anneal. The intermediate spacer is PECVD TEOS-SiO$_2$, with target thickness 450 nm corresponding to a target B-B distance of 850 nm. Layer 2 repeats the SiN core process, and the top cladding is PECVD TEOS-SiO$_2$ with stress management by stress release trenches and anneal as used for the spacer (Huang et al., 14 Apr 2026).

Stress control is integral to the process. High-temperature annealing at $_2$0C for 2 h in N$_2$1 is described as essential to reduce optical absorption; in the reported devices it boosts intrinsic $_2$2 from 0.066 M without anneal to approximately 5.2 M after anneal and mild CMP. Before each anneal, stress release trenches are etched into each newly deposited film to confine and localize tensile stress, reduce wafer bow, prevent crack propagation, and stabilize overlay and CMP uniformity. These trenches are patterned to avoid waveguide areas and large blank regions.

The fabrication is organized as a standardized five-step sequence iterated for each device layer: deposition, stress release trench formation, anneal, pattern/etch, and E-CMP planarization. Before spacer planarization, the Layer 1 SiN surface can itself receive a separate mild CMP, which reduces SiN RMS roughness from 1.05 nm to 0.29 nm before cladding deposition. The SiN etch uses a fluorine-based dry etch after photoresist reflow to reduce sidewall roughness. The process notes emphasize that E-CMP reduces CMP sensitivity to pattern density, while stress release trenches reduce lithography-related overlay sensitivity by controlling wafer bow (Huang et al., 14 Apr 2026).

3. Spacer uniformity, metrology, and wafer-scale control

The primary metrology quantity for the spacer is the B-B distance, defined as the distance between the bottoms of the Layer 1 and Layer 2 SiN cores. This definition reduces fitting uncertainty by minimizing multi-material stacks in the thickness model. Across a 4-inch wafer, the reported B-B distance has a measured mean of 872 nm, a coefficient of variation of 2.06%, and kurtosis $_2$3, versus a target of 850 nm. From the reported mean and coefficient of variation, the standard deviation is approximately $_2$4 nm, and a $_2$5 range of approximately 54 nm bounds the across-wafer variation (Huang et al., 14 Apr 2026).

The metrology suite combines qualitative and quantitative indicators. White-light interference imaging is used to visualize wafer-scale thickness uniformity, and the E-CMP wafer shows markedly uniform interference color relative to the CMP-only wafer. AFM and profilometry are used for roughness, yielding RMS values of approximately 0.2 nm for the E-CMP SiO$_2$6 spacer surface and 0.29 nm for the mildly polished SiN surface. The description of “fitting the film thickness” implies spectroscopic ellipsometry or reflectometry for quantitative thickness extraction.

Uniformity is not spatially perfect. Edge dies show increased deviation from design thickness, indicating a residual center-to-edge trend. The reported interpretation is that E-CMP substantially mitigates but does not fully eliminate edge trends. This residual nonuniformity is significant because, in vertically coupled SiN-on-SiN structures, spacer thickness sets the inter-layer coupling coefficient and therefore the transition loss distribution across dies. The process result is therefore not only a surface-planarity result but a coupling-uniformity result (Huang et al., 14 Apr 2026).

4. Inter-layer couplers, $_2$7-engineered tapers, and reliability

The device-level motivation for E-CMP is the reduction of spacer-thickness variation seen by inter-layer couplers. In the reported hybrid-ring extraction, inter-layer transition loss per coupler is obtained from

$_2$8

with $_2$9, corresponding to FSR $1{:}1$0 GHz. Aggregate wafer histograms give $1{:}1$1 mdB for the linear taper and 7.20 mdB for the $1{:}1$2-engineered taper. Die-to-die statistics report mean $1{:}1$3 mdB with CV 24.58% and $1{:}1$4 for the linear taper, versus 6.51 mdB with CV 9.69% and $1{:}1$5 for the $1{:}1$6-engineered taper. The best measured coupler is 5.56 mdB at wafer scale for the $1{:}1$7-engineered taper (Huang et al., 14 Apr 2026).

The baseline linear taper consists of two linear tapers that cross and are phase matched at a single point where the widths are equal. In this geometry, $1{:}1$8 is sharply peaked and narrow, so power transfer is abrupt and sensitive to small offsets. The $1{:}1$9-engineered taper starts from the linear taper, discretizes it into 20 segments, and remaps the local coupling coefficient of each segment onto a smooth Hermite-interpolated target $\mu$0. The remapping fixes the start, end, and phase-matched points, sets the first derivative at the phase-matched point to zero to flatten $\mu$1, enforces equal-and-opposite start and end derivatives for symmetry, and tunes a single slope parameter $\mu$2 to obtain a smooth transmission–length characteristic. This expands the “phase-matched point” into a broad “phase-matched area,” increasing $\mu$3 at fixed length and reducing sensitivity to spacer error $\mu$4 and lateral offset $\mu$5.

The coupled-mode description in the paper states that the local coupling coefficient typically follows $\mu$6, so spacer error perturbs $\mu$7 multiplicatively. Power transfer is written as

$\mu$8

and efficient transfer is associated with small $\mu$9 and large $_2$0 over an extended region. The robustness target is therefore to flatten $_2$1 around phase matching and keep $_2$2 near that region.

The paper further defines a dimensionless reliability metric

$_2$3

where $_2$4 is measured transmission, $_2$5 is taper length in $_2$6m, and $_2$7 is lateral offset in nm up to 600 nm. Across all 24 experimental groups with $_2$8–120 $_2$9m and $360^\circ$0–600 nm, the mean reliability is $360^\circ$1 versus $360^\circ$2, corresponding to a 75% improvement for the $360^\circ$3-taper. In the most severe condition, namely 20 $360^\circ$4m length and 600 nm lateral offset, the linear taper failed to produce a fittable resonance, while the $360^\circ$5-taper still achieved approximately 0.76 dB/coupler. The measured spectra are also flatter across 1480–1620 nm, indicating weaker wavelength dependence (Huang et al., 14 Apr 2026).

5. Waveguide loss and two-layer cavity formation

The planarization and stress-control strategy is tied directly to propagation loss. Across 21 dies on a 4-inch wafer, single-layer ring measurements over 1530–1620 nm yield most probable propagation losses of 0.077 dB/cm for Layer 1 and 0.068 dB/cm for Layer 2. The reported process-level basis for these values is the combination of PECVD SiN, high-temperature anneal, mild CMP of SiN to RMS 0.29 nm, and ultra-smooth SiO$360^\circ$6 produced by E-CMP at RMS approximately 0.2 nm (Huang et al., 14 Apr 2026).

Low vertical transition loss permits hybrid resonators that cross layers through two inter-layer tapers. These hybrid rings exhibit propagation losses of 0.170 dB/cm when implemented with linear tapers and 0.157 dB/cm when implemented with $360^\circ$7-engineered tapers, consistent with mdB-level taper losses extracted from the hybrid-ring formalism. The paper states that the low inter-layer loss enables the first class of 3D high-$360^\circ$8 optical cavities occupying two distinct device layers.

The cavity definition used is the standard intrinsic quality factor relation

$360^\circ$9

The reported result is high intrinsic $1150^\circ$0 across the telecom S, C, and L bands for single cavities spanning both layers. The stated interpretation is that vertical transition loss and spacer uniformity are sufficiently controlled that the hybrid cavities behave nearly like in-plane cavities; $1150^\circ$1 is dominated by waveguide propagation loss rather than by the vertical transitions. This shifts the limiting mechanism away from inter-layer interfaces and toward the baseline waveguide platform (Huang et al., 14 Apr 2026).

6. Scalability, comparative context, and process limits

The process is demonstrated at wafer scale on a standard 4-inch wafer, with 21 dies analyzed. The measurement set comprises 4385 resonances for Layer 1, 4430 for Layer 2, 4170 for hybrid rings with linear tapers, and 4074 for hybrid rings with $1150^\circ$2-engineered tapers, all measured over 1480–1620 nm with ultra-fine wavelength stepping. The tool set is conventional for integrated photonics fabrication: standard PECVD for SiN and TEOS-SiO$1150^\circ$3, ICP etch, CMP, and a nanoimprint lithography resist for step coverage. The process notes explicitly state that no exotic materials or sub-fab chemistries are required (Huang et al., 14 Apr 2026).

The thermal budget defines an important integration boundary. Deposition occurs at $1150^\circ$4C, but the critical film-purification step is the $1150^\circ$5C, 2 h N$1150^\circ$6 anneal repeated for each layer. This is described as front-end compatible but not back-end-of-line CMOS compatible without thermal-budget accommodations. Throughput is improved relative to CMP-dominated planarization because the bulk leveling is performed by the ICP etch-back, leaving one etch-back plus a short CMP cycle per spacer.

In comparative terms, the paper positions E-CMP between simpler but less uniform methods and more complex but highly planar methods. Relative to CMP-only processing, E-CMP suppresses visible interference nonuniformity and reduces die-to-die loss tails, particularly at wafer edges for linear tapers. Relative to Damascene CMP, it achieves low loss and uniformity with a simpler PECVD + stress release trench + E-CMP flow that is readily iterated for multilayers. Relative to spin-on planarization or pure etch-back, it reaches the approximately 0.2 nm RMS surface quality associated with the reported optical performance.

Residual risks remain. Edge roll-off and center-to-edge thickness trends persist to a limited extent, and extreme pattern-density contrast can still influence local oxide thickness during deposition and etch-back. As with any CMP process, micro-scratches and particles remain relevant, so short polish duration and proper pad conditioning are emphasized. The proven mitigations in the reported work are stress release trenches before every high-temperature anneal, NIL resist of approximately 600 nm for superior step coverage, ICP tuning to approximately $1150^\circ$7 selectivity between resist and oxide, short CMP targeted to smoothing, endpoint control via B-B distance metrology, and white-light interference imaging for rapid uniformity screening. The stated porting guideline is that the E-CMP principle—conformal cap, isorate etch-back, and short CMP—is applicable to SiN/SiO$1150^\circ$8, Si/SiO$1150^\circ$9, and AlN/SiO$_2$0 provided that the etch chemistry can be tuned to approximately $_2$1 selectivity to the chosen resist. A plausible implication is that the method’s broader utility depends less on the optical material itself than on the availability of a controllable isorate etch-back pair and on the tolerance requirements of the vertical coupler design (Huang et al., 14 Apr 2026).