Surface Participation Ratio in Qubits

• Surface Participation Ratio is a geometry-dependent metric that quantifies the fraction of a qubit’s electric-field energy stored in thin, lossy dielectric interfaces.
• It links electromagnetic field localization at metal–substrate, metal–air, and substrate–air interfaces to dielectric loss, impacting qubit quality factor and T1.
• Advanced simulations and design optimizations reduce participation ratios, yielding measurable improvements in coherence for superconducting transmon devices.

Surface participation ratio is a geometry-dependent measure of how much of a superconducting qubit’s electric-field energy resides in thin, lossy dielectric layers at interfaces such as metal–substrate (MS), metal–air (MA), and substrate–air (SA). In transmons, those layers may contain oxides, adsorbates, or other microscopic defects that act as two-level systems (TLS), absorb energy from the oscillating field, and thereby limit the quality factor and the relaxation time $T_1$. The quantity is therefore the standard bridge between electromagnetic field localization, interface loss, and coherence engineering in superconducting quantum circuits (Wang et al., 2015, Eun et al., 2022).

1. Definition and physical content

For a lossy material or interface $i$, the participation ratio is defined as the fraction of total electric-field energy stored in that region. In volume form,

$$p_i=\frac{\displaystyle \int_{V_i} \frac{1}{2}\,\epsilon_i |\mathbf{E}|^2\, dV}{\displaystyle \int_{\text{all space}} \frac{1}{2}\,\epsilon |\mathbf{E}|^2\, dV}.$$

This definition is general: it identifies the energetic weight of a specified dielectric region relative to the full mode energy. In superconducting qubits, it is most often applied to interfacial layers that are only a few nanometers thick but sit in locations where the electric field is large (Wang et al., 2015).

For thin interface layers, the same idea is recast as a surface quantity. One formulation writes

$$p_i=\frac{t_i\varepsilon_i/2}{W}\int_i dS\,|E_i|^2,$$

where $W$ is the total stored electric energy of the mode, and $t_i$ and $\varepsilon_i$ are the thickness and dielectric constant of the interfacial layer. This thin-layer approximation replaces the volume integral by a surface integral because the interface thickness is negligible compared with the lateral device scale. In that approximation, $p_i$ is directly interpreted as the fraction of the qubit’s electric energy exposed to a specific interfacial loss channel, so reducing $p_i$ reduces dielectric exposure to TLS defects (Eun et al., 2022).

The physical importance of the metric follows from field concentration. Even when an interfacial layer occupies a tiny geometric volume, it can contribute disproportionately to loss if it sits near metal edges, narrow leads, or the junction region, where $|\mathbf E|^2$ is large. Surface participation ratio is therefore not a measure of geometric area or volume alone; it is an energy-localization metric weighted by the actual mode profile (Wang et al., 2015).

2. Relation to dielectric loss, quality factor, and $i$0

The participation-ratio model enters dielectric-loss theory through a weighted sum over interfacial channels. One standard expression is

$i$1

where $i$2 is the participation ratio of interface $i$3 and $i$4 is that layer’s loss tangent. The inverse TLS-limited quality factor is therefore the sum of each interface’s energetic participation multiplied by its intrinsic dissipation (Eun et al., 2022).

An equivalent decay-rate formulation writes

$i$5

with $i$6, or

$i$7

This representation separates geometry-dependent dielectric loss from any geometry-independent residual channel $i$8. If one interface dominates and its loss tangent is approximately constant across devices, then the relaxation rate is expected to scale approximately linearly with that interface participation, $i$9 (Wang et al., 2015).

This scaling is not merely formal. In 3D-cavity transmons with a clean electromagnetic environment and suppressed non-equilibrium quasiparticles, an approximately proportional relation was found between measured transmon relaxation rates and simulated surface participation ratios. That result supports the conclusion that surface/interface dielectric dissipation is a major limiting factor for $$p_i=\frac{\displaystyle \int_{V_i} \frac{1}{2}\,\epsilon_i |\mathbf{E}|^2\, dV}{\displaystyle \int_{\text{all space}} \frac{1}{2}\,\epsilon |\mathbf{E}|^2\, dV}.$$0 in that architecture (Wang et al., 2015).

A central reason surface layers matter is that they combine small participation with relatively large intrinsic loss. Bulk crystalline substrates can store a large fraction of total electric energy while maintaining very low loss tangents, whereas thin surface layers may have loss tangents on the order of $$p_i=\frac{\displaystyle \int_{V_i} \frac{1}{2}\,\epsilon_i |\mathbf{E}|^2\, dV}{\displaystyle \int_{\text{all space}} \frac{1}{2}\,\epsilon |\mathbf{E}|^2\, dV}.$$1–$$p_i=\frac{\displaystyle \int_{V_i} \frac{1}{2}\,\epsilon_i |\mathbf{E}|^2\, dV}{\displaystyle \int_{\text{all space}} \frac{1}{2}\,\epsilon |\mathbf{E}|^2\, dV}.$$2. Consequently, interfacial layers can dominate total loss despite nanometer-scale thickness (Wang et al., 2015).

3. Multiscale computation and analytical reduction

Accurate evaluation of surface participation ratio is a multiscale problem. Practical devices span millimeter-scale cavities or packages, micron-scale electrodes, and nanometer-scale lossy layers, while the field itself is strongly enhanced at sharp conductor edges. A brute-force 3D simulation with nanometer resolution everywhere is therefore computationally impractical (Wang et al., 2015).

One established solution is a two-step finite-element workflow. A coarse global 3D simulation captures the large-scale electric-field distribution of the qubit–cavity system away from singular regions, and separate local fine simulations resolve representative edge and junction environments with sub-nanometer resolution. In the 3D transmon study, this meant a coarse full-system solve, a 2D cross-section near metal edges, and a local 3D model near the Josephson junction and lead region. The local scaling behavior near edges is then combined with the global field to reconstruct total surface participation (Wang et al., 2015).

Analytical work for coplanar architectures reformulates the same problem through conformal mapping. In that framework, the electrostatic field of coplanar capacitor and coplanar waveguide geometries is solved in 2D, and the energy in a thin interfacial region is reduced from a singular volume integral to a contour integral using Green’s identity,

$$p_i=\frac{\displaystyle \int_{V_i} \frac{1}{2}\,\epsilon_i |\mathbf{E}|^2\, dV}{\displaystyle \int_{\text{all space}} \frac{1}{2}\,\epsilon |\mathbf{E}|^2\, dV}.$$3

This reduction yields exact or approximate expressions for $$p_i=\frac{\displaystyle \int_{V_i} \frac{1}{2}\,\epsilon_i |\mathbf{E}|^2\, dV}{\displaystyle \int_{\text{all space}} \frac{1}{2}\,\epsilon |\mathbf{E}|^2\, dV}.$$4, $$p_i=\frac{\displaystyle \int_{V_i} \frac{1}{2}\,\epsilon_i |\mathbf{E}|^2\, dV}{\displaystyle \int_{\text{all space}} \frac{1}{2}\,\epsilon |\mathbf{E}|^2\, dV}.$$5, and $$p_i=\frac{\displaystyle \int_{V_i} \frac{1}{2}\,\epsilon_i |\mathbf{E}|^2\, dV}{\displaystyle \int_{\text{all space}} \frac{1}{2}\,\epsilon |\mathbf{E}|^2\, dV}.$$6, clarifies the logarithmic shallow-depth dependence of thin-layer participation, and avoids the failure mode of naïve volumetric FEM near singular edges (Murray et al., 2017).

More recent computational development retains the same physical metric while changing the numerical formulation. The simulator SesQ is a surface integral equation method tailored to energy participation ratio calculations in superconducting qubits. It discretizes only 2D conductor surfaces, uses a semi-analytical multilayer Green’s function, applies non-conformal boundary mesh refinement near edges, and evaluates thin-layer energy with quadrature across the contamination thickness rather than the approximation $$p_i=\frac{\displaystyle \int_{V_i} \frac{1}{2}\,\epsilon_i |\mathbf{E}|^2\, dV}{\displaystyle \int_{\text{all space}} \frac{1}{2}\,\epsilon |\mathbf{E}|^2\, dV}.$$7. In its reported benchmarks, it accelerates capacitance extraction by roughly two orders of magnitude relative to commercial FEM, achieves comparable capacitance accuracy, and reports larger participation ratios in practical transmons, supporting the claim that conventional FEM can significantly underestimate EPR when edge singularities and nanometer-thin layers are underresolved (Wang et al., 30 Mar 2026).

4. Edge singularities, local decomposition, and near-junction physics

The main technical complication in surface participation calculations is the singular electric field near conductor corners and edges. In both analytical and numerical treatments, $$p_i=\frac{\displaystyle \int_{V_i} \frac{1}{2}\,\epsilon_i |\mathbf{E}|^2\, dV}{\displaystyle \int_{\text{all space}} \frac{1}{2}\,\epsilon |\mathbf{E}|^2\, dV}.$$8 becomes large enough near those locations that direct evaluation of $$p_i=\frac{\displaystyle \int_{V_i} \frac{1}{2}\,\epsilon_i |\mathbf{E}|^2\, dV}{\displaystyle \int_{\text{all space}} \frac{1}{2}\,\epsilon |\mathbf{E}|^2\, dV}.$$9 is ill-conditioned or mesh-sensitive. Surface participation ratio is therefore inseparable from a regularization or decomposition strategy (Murray et al., 2017).

One transmon-specific implementation splits the capacitor pad into an interior region and a perimeter region, then further divides the perimeter into an “accurate” part and a “diverging” near-edge part. The interior and accurate perimeter fields are computed directly by finite-element simulation, while the near-edge contribution is estimated with a scaling factor $$p_i=\frac{t_i\varepsilon_i/2}{W}\int_i dS\,|E_i|^2,$$0 obtained from the ratio of energy in the accurate and diverging regions. This reconstruction is designed to recover the total pad participation even though the local field diverges at the edge (Eun et al., 2022).

The junction wire is treated separately because its geometry is narrow and localized near the Josephson junction. Under the assumption that junction-wire participation is approximately independent of capacitor-pad shape when the wire remains much smaller than pad features, the wire can be modeled with the flat-coax approximation from Martinis et al. In that model, the electric energy is approximated by

$$p_i=\frac{t_i\varepsilon_i/2}{W}\int_i dS\,|E_i|^2,$$1

where $$p_i=\frac{t_i\varepsilon_i/2}{W}\int_i dS\,|E_i|^2,$$2 is the field along the wire centerline, $$p_i=\frac{t_i\varepsilon_i/2}{W}\int_i dS\,|E_i|^2,$$3 is the local half-width, $$p_i=\frac{t_i\varepsilon_i/2}{W}\int_i dS\,|E_i|^2,$$4 is the dielectric thickness, and the “$$p_i=\frac{t_i\varepsilon_i/2}{W}\int_i dS\,|E_i|^2,$$5” term is a thickness correction factor. This converts a localized 3D field problem into a practical 1D energy estimate (Eun et al., 2022).

A distinct issue arises in the region very close to the junction. In experimental participation–loss analysis, the contribution from within about $$p_i=\frac{t_i\varepsilon_i/2}{W}\int_i dS\,|E_i|^2,$$6 of the junction was found to be nearly geometry-independent; including it in the participation accounting produced an unphysical fit with a negative intercept. Excluding that sub-micron region restored a physically sensible proportionality between $$p_i=\frac{t_i\varepsilon_i/2}{W}\int_i dS\,|E_i|^2,$$7 and participation. The interpretation offered was spatial discreteness of surface dielectric dissipation: a very small region may contain no resonant TLS at all, even if classical field theory assigns it nonzero participation. That argument does not reject participation-ratio modeling, but it limits the assumption that every infinitesimal high-field region is uniformly lossy (Wang et al., 2015).

5. Geometry engineering and shape optimization

Because surface participation ratio is explicitly geometry-dependent, it can be used as an optimization target. In one transmon design study, both capacitor pad and junction wire were parameterized by B-splines, and the spline control points were optimized with the DIRECT global optimization algorithm. The capacitor-pad optimization used eight design variables, the junction-wire optimization used four, and the electromagnetic evaluations were performed with HFSS eigenmode simulations. The pad optimization stopped when either 360 function evaluations were reached or a dynamic convergence criterion was satisfied (Eun et al., 2022).

The optimization objective was chosen to track the dominant loss channel while preserving transmon operating constraints. For the capacitor pad, the objective function was the MS participation ratio of the interior region, motivated by a parametric sweep showing that interior and perimeter participation tend to move together for the floating transmons studied. A penalty constrained the charging energy $$p_i=\frac{t_i\varepsilon_i/2}{W}\int_i dS\,|E_i|^2,$$8 to remain below $$p_i=\frac{t_i\varepsilon_i/2}{W}\int_i dS\,|E_i|^2,$$9 MHz so that the anharmonicity stayed in a reasonable range, and the footprint was also constrained. For the junction wire, the objective was again the MS participation computed from the centerline field $W$0 (Eun et al., 2022).

The reported reductions were specific and substantial. For the capacitor pad, the optimized design achieved $W$1 ppm, compared with $W$2 ppm for a previous double-pad geometry and $W$3 ppm for a concentric transmon. This corresponds to roughly a $W$4 reduction relative to the double-pad reference, with about $W$5–$W$6 reduction across $W$7. For the junction wire, the optimized geometry yielded $W$8 ppm, compared with $W$9 ppm for a straight wire and $t_i$0 ppm for a linear taper, or roughly a $t_i$1 reduction relative to the straight wire. The optimized wire resembled a tapered wire with a narrow neck in the middle, which reduced local electric-field concentration (Eun et al., 2022).

These participation reductions mapped directly onto predicted coherence gains. Using dielectric parameters from the literature, the reference design with a double-pad capacitor and straight wire gave

$t_i$2

whereas the optimized pad plus optimized wire gave

$t_i$3

The increase of approximately $t_i$4 in both TLS-limited quality factor and relaxation time illustrates the role of surface participation ratio as the objective metric connecting electromagnetic shape engineering to qubit coherence (Eun et al., 2022).

6. Trenching, broader design use, and terminological boundaries

Surface participation ratio also underlies substrate-trenching studies in coplanar resonators and qubits. An analytical treatment based on conformal mapping showed that trenching changes participation in two regimes. At very shallow trench depth, total SA participation can initially increase because the trench introduces sidewalls close to strong edge fields; the sidewall contribution was reported to saturate around $t_i$5 nm. At larger trench depths, overall participation decreases because trenching reduces the effective dielectric loading and thus the electric energy stored in lossy surface layers. The same framework was extended from CPW resonators to coplanar capacitors relevant to transmons (Murray, 2020).

That analysis also connected participation modeling to experiment. For trenched CPW resonators on silicon, assuming SA loss dominance and fitting

$t_i$6

a linear least-squares fit gave

$t_i$7

with $t_i$8 within fitting uncertainty. In the representative qubit geometry treated in the same work, SA participation started from the untrenched value $t_i$9, then exhibited the same shallow-depth increase and larger-depth decrease seen in the CPW case (Murray, 2020).

A recurring misconception is terminological rather than physical. In superconducting-circuit literature, surface participation ratio refers specifically to electric-field energy stored in thin lossy interfaces. That notion is distinct from the ordinary participation ratio used in many-body spectral analysis, Floquet-state delocalization, condensation of random variables, or gradient concentration in adversarial training. Several papers in those areas explicitly do not define a surface participation ratio, even though they use the phrase “participation ratio” for basis-space, phase-space, or coordinate-space localization measures. The shared label therefore does not imply a shared observable (Beugeling et al., 2014, Duque et al., 20 Feb 2026, Gradenigo et al., 2017, Mehouachi et al., 5 May 2025).

Within superconducting qubits, the central design conclusion remains stable across simulation, analytics, and optimization studies: surface participation ratio is the operative metric linking device geometry to TLS-induced dielectric loss. Lowering it does not by itself improve materials, remove all non-dielectric decay channels, or guarantee uniform TLS statistics near the junction, but it directly reduces the fraction of mode energy stored in the thin interfacial layers most strongly associated with decoherence (Wang et al., 2015, Eun et al., 2022).