Interdigitated Shunting Capacitors in Quantum Circuits

Updated 24 February 2026

Interdigitated shunting capacitors are planar structures with interleaved electrodes that precisely engineer capacitance for applications in superconducting quantum circuits and microwave devices.
The design improvements enable enhanced qubit coherence and tunable coupling, with measured T1 increases and coupling adjustments from ~25 MHz to below 10 kHz validated by both simulations and analytic models.
Analytical techniques like conformal mapping and EM simulation guide design optimization, establishing scaling laws and material strategies to minimize dielectric loss and parasitic effects.

Interdigitated shunting capacitors (IDCs) are planar capacitive structures composed of multiple interleaved "finger" electrodes, typically fabricated on substrates such as Si or sapphire, with wide application in superconducting quantum circuits, coplanar filter banks, and microwave resonators. Their defining feature—arrays of alternating, coplanar metallic bands—enables precise engineering of capacitance while retaining compatibility with large-scale lithography. In quantum device contexts, IDCs serve as the dominant shunting element in charge-insensitive transmon qubits, couplers, and other circuit elements where large, well-defined capacitance, low loss, and robust tolerance to spurious coupling are critical (Li et al., 4 Mar 2025, Chang et al., 2013, Yévenes et al., 2021).

1. Geometric and Material Foundations

An IDC comprises two sets of parallel metallic fingers, each set connected to a common electrode, interleaved with one another and separated by a defined gap. The main geometric parameters are finger width $w$ , inter-finger gap $g$ , finger length $l$ , number of fingers per side $N$ , and substrate thickness $h$ . Material choices for electrodes (Al, TiN, Nb, NbN, etc.) and substrates (Si, sapphire) directly impact dielectric loss, kinetic inductance effects, and compatibility with standard processes.

Typical geometries: $w, g$ in the range of 2–40 μm, $l$ in the 100–200 μm regime, $N$ often 10–20 per electrode (Chang et al., 2013, Li et al., 4 Mar 2025).
Film and interface quality are critical: For instance, 30 nm TiN grown on HF-terminated Si with a 2 nm SiN buffer yields minimal two-level system (TLS) loss (Chang et al., 2013).
For a deep (semi-infinite) substrate, total capacitance per finger:

$C_{\rm IDC} \approx 2(N-1)\varepsilon_0\varepsilon_{\rm eff}\frac{K(k)}{K(k')}l$

with $k = w/(w+2g)$ and $K$ the complete elliptic integral of the first kind (Yévenes et al., 2021).

For rapid scaling estimates: $C_{\rm IDC} \approx \varepsilon_0\varepsilon_{\rm eff}\frac{N\,l}{g}$ (fringing correction $\sim$ 10–20%) (Chang et al., 2013).

2. Principles of Capacitance Determination

Capacitance in IDCs is shaped by both the geometry and the electromagnetic environment, notably including fringing electric fields that substantially enhance effective capacitance over naive parallel-plate estimates.

For arbitrary slab thickness, the capacitance per unit length is rigorously given by

$C' = 2\varepsilon\frac{K'(k_\rho)}{K(k_\rho)}$

where $k_\rho$ depends parametrically on $(w, g, h)$ via conformal mapping (Yévenes et al., 2021).

Deep substrate ( $h \gg w+g$ ):

$C'_{\rm deep} \approx \frac{2\varepsilon}{\pi}\ln\left(\frac{8(w+g)}{\pi g}\right)$

which remains accurate to within 5% for $g/(w+g) < 0.56$ .

Shallow substrate ( $h \lesssim w+g$ ): explicit formulas in terms of $\tanh$ and $\sinh$ functions yield accurate results (Yévenes et al., 2021).
Fringing corrections and end effects can be systematically computed and typically contribute less than 2% for $N > 10$ (Yévenes et al., 2021).

3. Implementation in Quantum and Microwave Circuits

IDCs are central to numerous superconducting device applications, with demonstrated performance advantages in both qubit coherence and coupling control.

In capacitively-shunted double-transmon couplers, an IDC (8 fingers per side, $w=4$ μm, $g=2$ μm, $l=100$ μm, Nb film) achieves $C_{34}=78\pm2$ fF, matching both 3D EM simulation (Ansys HFSS, $80$ fF) and analytic formulas (parallel-plate and fringing, $75$ fF) to within 5% (Li et al., 4 Mar 2025).
The IDC enables on/off exchange coupling tuning from $\sim$ 25 MHz to $<$ 10 kHz (zero DC bias), with residual ZZ shift $|\zeta_{\rm off}/2\pi| \leq 35.4$ kHz and high-fidelity (99.89%) CZ gates. Quality factors $Q > 10^5$ and $T_1 > 10\,\mu$ s are maintained at operational points (Li et al., 4 Mar 2025).
In single-transmon devices, TiN IDCs ( $w=g=30$ μm) enable $T_1 = 53$ – $55\,\mu$ s and $T_2^{*}=56$ – $58\,\mu$ s, with evidence that losses are dominated by surface participation rather than bulk dielectric or metal (Chang et al., 2013).

Application	Geometry/Material	Key Performance
Double-transmon coupler	8×4 μm/2 μm Nb IDC	$C=78$ fF, tunable $g$ , $T_1>10\,\mu$ s
Planar transmon	$w,g=30\,\mu$ m TiN	$T_1=55\,\mu$ s, $Q\sim 10^6$

4. Analytical and Numerical Modeling Techniques

Conformal mapping and EM simulation provide principle tools for computing and validating IDC characteristics.

The conformal-mapping approach maps the interdigitated array to an equivalent parallel-plates domain using elliptic functions, fully capturing the effect of geometry, domain height, and fringing fields for both infinite and finite arrays (Yévenes et al., 2021).
Closed-form results are available for special cases; series expansion (nome approximation) allows for elementary approximation with error bounds (Yévenes et al., 2021).
EM solvers (e.g., Ansys HFSS) provide full 3D field solutions, with measured capacitances agreeing at the $\sim$ 5% level with analytic predictions (Li et al., 4 Mar 2025).

5. Design Optimization and Scaling Laws

Design of high-coherence IDCs is governed by both geometric and material considerations, subject to constraints from loss mechanisms and process compatibility.

For a fixed capacitance, total electrode area is minimized for $w=g$ , i.e., equal finger and gap widths (Yévenes et al., 2021).
$T_1$ increases monotonically with increasing $w$ (and $g$ ), due to reduced surface participation, with empirical scaling $T_1 \propto w^\alpha$ , $\alpha \approx 1$ where surface TLS dominate (Chang et al., 2013).
To suppress losses, use $w, g \geq 40\,\mu$ m if layout allows, employ thick ( $>30$ nm) high- $T_c$ films (e.g., TiN), optimize sidewall smoothness, and maintain ultra-clean interfaces by in situ plasma treatment and sacrificial dielectric capping (Chang et al., 2013).
Parasitic slotline modes are suppressed by enforcing $l$ short enough to push the first resonance above 15 GHz, and ground return structure/air bridges further mitigate mode conversion (controlling radiative and crosstalk losses) (Li et al., 4 Mar 2025).

6. Fringe Effects, End Corrections, and Practical Recommendations

End-finger capacitance ( $C'_{\rm end}$ ) is smaller than interior fingers; the closed-form formula for $C'_{\rm end}$ involves elliptic integrals for the end-cell width of $2(w+g)$ (Yévenes et al., 2021).
These corrections become negligible ( $<$ 2%) when $N\gtrsim 10$ .
For high-accuracy needs ( $<5\%$ error), always solve the full conformal-mapping/elliptic-integral formulas; otherwise, the deep/shallow substrate approximations suffice.
For target $C'$ , select geometry to have $w=g$ and $h/(w+g)\gtrsim 1$ .
Validate performances by correlation between measured, analytic, and simulated capacitance values within 5% (Li et al., 4 Mar 2025, Yévenes et al., 2021).

7. Impact on Quantum Device Coherence and Outlook

The transition from traditional Al to engineered TiN IDCs, with optimized geometry and surface treatments, has yielded up to sixfold improvements in $T_1$ for planar transmons ( $T_1$ from 18 μs to 55 μs), conclusively attributing leading losses to surface TLS participation (Chang et al., 2013). High-quality IDCs now allow planar circuit QED devices to approach the coherence benchmarks formerly exclusive to 3D cavity-based designs. Ongoing advances in material engineering, conformal modeling, and EM validation are expected to further suppress residual decoherence and enable even higher precision in coupling and control elements incorporating interdigitated shunting capacitors.

References:

(Li et al., 4 Mar 2025): Capacitively Shunted Double-Transmon Coupler Realizing Bias-Free Idling and High-Fidelity CZ Gate
(Chang et al., 2013): Improved superconducting qubit coherence using titanium nitride
(Yévenes et al., 2021): Analytical solution for two-dimensional Laplace's equation in a shallow domain containing coplanar interdigitated boundaries