Superconducting Erasure Qubits

• Superconducting erasure qubits are defined by embedding logical states within a higher-dimensional Hilbert space, enabling physical errors like relaxation and photon loss to be converted into detectable erasure events.
• Dual-rail, qutrit, and fluxonium architectures employ hardware-efficient detection protocols that map decoherence errors into flagged leakage states, significantly boosting error correction thresholds.
• Advances in pulse-shaping, ancilla control, and joint-photon number-splitting facilitate integration with high-performance error correction codes, achieving logical error rates below 10⁻⁵.

Superconducting erasure qubits are quantum hardware primitives that enable error correction schemes to convert the dominant physical error channel—notably relaxation (amplitude damping) and photon loss—into flagged erasure events, greatly enhancing the efficiency and threshold of quantum error correction protocols. By engineering the system Hilbert space and control hardware so that detectable “leakage” out of the computational subspace can be heralded, these devices transform state-of-the-art circuit QED platforms into high-threshold, resource-efficient substrates for fault-tolerant quantum information processing. Dual-rail cavity and transmon implementations, as well as hardware-efficient single-qutrit and fluxonium variants, span a breadth of superconducting architectures (Graaf et al., 2024, Huang et al., 16 Apr 2025, Liu et al., 9 Apr 2026, Violaris et al., 5 Jan 2026).

1. Principles of Erasure Qubit Encoding

A superconducting erasure qubit is defined by two characteristics: (i) its logical subspace is embedded in a higher-dimensional Hilbert space such that the dominant decoherence mechanism maps computational states into an orthogonal “erasure” subspace, and (ii) hardware-level measurements detect occupation of this erasure subspace, providing real-time error flags (Kubica et al., 2022, Violaris et al., 5 Jan 2026). In the prevalent dual-rail encoding, two physical modes (transmons, cavity modes, or fluxonia) jointly carry a logical qubit.

Dual Rail Encoding Formalism

For two modes (labeled $a$, $b$), the logical basis is

$$|0_L\rangle = |1_a, 0_b\rangle, \quad |1_L\rangle = |0_a, 1_b\rangle.$$

Amplitude damping (photon loss or qubit relaxation on either rail) moves the state to $|0_a, 0_b\rangle$, orthogonal to the codespace. Detecting $|0,0\rangle$ thus heralds an erasure event. The underlying Kraus operators for physical amplitude-damping with per-rail probability $\gamma$ are

$$K_0 = \sqrt{1-\gamma}\,I_\text{logical},\quad K_1 = |00\rangle\langle01|\,\sqrt{\gamma},\quad K_2=|00\rangle\langle10|\,\sqrt{\gamma},$$

mapping logical states into the erasure state $|00\rangle$ (Violaris et al., 5 Jan 2026).

Alternate architectures encode the erasure subspace into higher excited levels of a single transmon (e.g., $|g\rangle$–$|f\rangle$ code, with $b$0 as the leakage level), or in the $b$1–$b$2 manifold of a fluxonium, where relaxation proceeds via a detectable intermediate state (Liu et al., 9 Apr 2026, Liu et al., 16 Jan 2026).

2. Device Architectures and Erasure Detection Protocols

Superconducting erasure qubits have been realized across several architectures, most notably:

Dual-Rail Cavity Qubits

High-$b$3 3D cavities, such as $b$4 stub or double-post designs, coupled by parametric (e.g., SNAIL-based) beamsplitter elements and monitored by dispersively coupled transmons, provide robust dual-rail erasure qubits (Graaf et al., 2024, Koottandavida et al., 2023, Chou et al., 2023). Erasure detection is achieved by mapping the joint photon number (e.g., $b$5) onto the ancilla state, using techniques such as Ramsey interferometry or selective $b$6-pulses. The "joint-photon number-splitting" regime allows a single ancilla-transmon, dispersively coupled to one rail, to serve both single-qubit and erasure-detection operations with minimal device overhead (Graaf et al., 2024).

Dual-Rail Transmon Qubits

Pairs of strongly coupled transmons serve as the logical rails, with mid-circuit erasure checks implemented via dispersive ancilla readout or multi-qubit joint measurements (Huang et al., 16 Apr 2025, Violaris et al., 5 Jan 2026). The logical subspace is either in the $b$7 basis or the single-excitation manifold antisymmetrizations. Leakage to $b$8 is detected via cavity or transmission line measurements.

Qutrit and Fluxonium Erasure Qubit Implementations

A single transmon operated as a qutrit encodes the logical states in the $b$9 and $$|0_L\rangle = |1_a, 0_b\rangle, \quad |1_L\rangle = |0_a, 1_b\rangle.$$0 levels, with relaxation to and detection of $$|0_L\rangle = |1_a, 0_b\rangle, \quad |1_L\rangle = |0_a, 1_b\rangle.$$1 as the heralded erasure channel. Fast SWAP-based erasure detection between the data qutrit and an ancilla, followed by ancilla readout, enables high-fidelity erasure flagging (Liu et al., 9 Apr 2026). Fluxonium devices at zero flux encode logical information in $$|0_L\rangle = |1_a, 0_b\rangle, \quad |1_L\rangle = |0_a, 1_b\rangle.$$2–$$|0_L\rangle = |1_a, 0_b\rangle, \quad |1_L\rangle = |0_a, 1_b\rangle.$$3, with population of $$|0_L\rangle = |1_a, 0_b\rangle, \quad |1_L\rangle = |0_a, 1_b\rangle.$$4 serving as an unambiguous signature of qubit relaxation and acting as the erasure flag (Liu et al., 16 Jan 2026).

Summary Table: Architectures

Device	Logical Encoding	Erasure Flag
Dual-rail cavity	$$|0_L\rangle = |1_a, 0_b\rangle, \quad |1_L\rangle = |0_a, 1_b\rangle.$$5, $$|0_L\rangle = |1_a, 0_b\rangle, \quad |1_L\rangle = |0_a, 1_b\rangle.$$6	$$|0_L\rangle = |1_a, 0_b\rangle, \quad |1_L\rangle = |0_a, 1_b\rangle.$$7
Dual-rail transmon	$$|0_L\rangle = |1_a, 0_b\rangle, \quad |1_L\rangle = |0_a, 1_b\rangle.$$8, $$|0_L\rangle = |1_a, 0_b\rangle, \quad |1_L\rangle = |0_a, 1_b\rangle.$$9	$|0_a, 0_b\rangle$0
Transmon qutrit	$|0_a, 0_b\rangle$1, $|0_a, 0_b\rangle$2	$|0_a, 0_b\rangle$3
Fluxonium	$|0_a, 0_b\rangle$4, $|0_a, 0_b\rangle$5	$|0_a, 0_b\rangle$6

3. Error Hierarchies, Noise Models, and Performance Metrics

Erasure-biased noise is characterized by dominant detectable erasure events and strongly suppressed in-subspace ("Pauli") errors. In leading implementations, erasure rates per erasure check range from $|0_a, 0_b\rangle$7 (dual-rail cavity) to $|0_a, 0_b\rangle$8 (dual-rail transmon), with Pauli error rates an order of magnitude below and missed-erasure probabilities at $|0_a, 0_b\rangle$9 or better (Graaf et al., 2024, Huang et al., 16 Apr 2025, Chou et al., 2023).

Typical error rates for dual-rail cavity implementations (Graaf et al., 2024):

Metric	Value
Missed-erasure (per check) $|0,0\rangle$0	$|0,0\rangle$1
Erasure rate (per check) $|0,0\rangle$2	$|0,0\rangle$3
Logical Pauli error (per check) $|0,0\rangle$4	$|0,0\rangle$5

Residual error channels after post-selecting "no erasure" are overwhelmingly dephasing (Pauli-Z) with bit-flip (Pauli-X) rates typically negligible $|0,0\rangle$6.

Erasure-detectable gates, notably parametric SWAP-based CZ entangling gates, can preserve the favorable error bias: per-gate erasure rates $|0,0\rangle$7, Z-error rates $|0,0\rangle$8, X-error rates $|0,0\rangle$9 (Mehta et al., 13 Mar 2025).

4. Quantum Error Correction and Thresholds

Erasure qubit architectures permit efficient concatenation with outer stabilizer codes such as the surface code or Floquet codes, greatly enhancing logical fidelity and reducing resource overhead. For heralded erasure error models, threshold erasure rates for surface codes can reach up to 5–7%, a factor of $\gamma$0 that for depolarizing Pauli noise (Gu et al., 2024, Chang et al., 2024). Under realistic circuit noise and imperfect erasure checks, thresholds in the 4–5% range remain achievable, with reduced effective distance only in unfavorable leakage-spreading scenarios.

Logical error rates for distance-$\gamma$1 codes under pure erasure bias scale as $\gamma$2, where $\gamma$3 is the erasure threshold. In mixed pauli-erasure settings, performance interpolates between the Pauli and erasure regimes (Gu et al., 2024). Empirical surface-code thresholds from union-find decoding with imperfect (built-in ancilla) erasure checks are summarized as follows (Chang et al., 2024):

Noise Model	Erasure Threshold (typical)
Pauli-only	$\gamma$4
Dual-rail w/ perfect ECs	$\gamma$5
Dual-rail, realistic ECs	$\gamma$6 (spatial $\gamma$7 temporal imperfection)

The ability to spatially and temporally resolve leaked qubits enables efficient minimum-weight perfect matching (or tailored decoders) which exploit erasure-flag locality (Gu et al., 2023, Chang et al., 2024).

5. Scaling, Control, and Engineering Developments

Recent developments have dramatically improved device performance and hardware efficiency:

• Hardware-Efficient Detection: Pulse-shaping and parametric coupler engineering (SNAIL, flux-tunable bridges) yield erasure checks with minimal extra overhead. Single-ancilla control of multiple modes and joint-photon-number-splitting regimes allow compact multi-qubit schemes (Graaf et al., 2024).
• Dynamical Error Reshaping: STIRAP-based pulse sequences for erasure detection and geometric-curve-engineered sideband modulation for two-qubit gates can suppress erasure-check and gate-induced errors by several orders of magnitude, matching or exceeding cavity-lifetime-limited performance (Dakis et al., 9 Oct 2025).
• Ancilla-Efficiency: Qutrit and fluxonium schemes demonstrate erasure conversion with no extra non-data qubits beyond those already required for measurement; dual-purposing ancillae for both erasure and parity checks allows further circuit simplification (Liu et al., 9 Apr 2026, Liu et al., 16 Jan 2026).
• Collective Erasing and Scaling: Superconducting erasing-head architectures permit fast, programmable reset of multiple qubits (reset times $\gamma$8 ns), with super-radiant enhancement for symmetric states and engineered avoidance of decoherence-free subspaces (Diniz et al., 2024). Cooperative quantum erasure demonstrated on quantum annealers can initialize large arrays of qubits at the Landauer limit (Buffoni et al., 2022).

6. Integration with High-Performance Codes and Outlook

Superconducting erasure qubits are a primary component in prototype stacked architectures that combine an inner, hardware-occurring erasure code (dual-rail, qutrit, or fluxonium) with high-threshold, erasure-aware surface codes or Floquet codes (Gu et al., 2023, Violaris et al., 5 Jan 2026). Simulations and experiments indicate:

• Logical error rates below $\gamma$9 at physical erasure rates $$K_0 = \sqrt{1-\gamma}\,I_\text{logical},\quad K_1 = |00\rangle\langle01|\,\sqrt{\gamma},\quad K_2=|00\rangle\langle10|\,\sqrt{\gamma},$$0 and Pauli errors in the $$K_0 = \sqrt{1-\gamma}\,I_\text{logical},\quad K_1 = |00\rangle\langle01|\,\sqrt{\gamma},\quad K_2=|00\rangle\langle10|\,\sqrt{\gamma},$$1 range.
• Coherence time enhancement by factors of $$K_0 = \sqrt{1-\gamma}\,I_\text{logical},\quad K_1 = |00\rangle\langle01|\,\sqrt{\gamma},\quad K_2=|00\rangle\langle10|\,\sqrt{\gamma},$$2 when post-selecting on erasure-free runs.
• Immediate applicability in early fault-tolerant hardware, with substantial overhead reduction (10–100$$K_0 = \sqrt{1-\gamma}\,I_\text{logical},\quad K_1 = |00\rangle\langle01|\,\sqrt{\gamma},\quad K_2=|00\rangle\langle10|\,\sqrt{\gamma},$$3 fewer physical qubits per logical qubit) relative to conventional Pauli-limited approaches.

Open engineering and theory questions include optimizing erasure-check frequency vs. induced error, further integrating erasure detection with measurement hardware, extending protocols to multi-rail/bosonic codes, and extending control protocols for low-crosstalk, high-rate operation in large arrays.

7. Summary of Representative Implementations and Metrics

Architecture	Tuning/Control	$$K_0 = \sqrt{1-\gamma}\,I_\text{logical},\quad K_1 = |00\rangle\langle01|\,\sqrt{\gamma},\quad K_2=|00\rangle\langle10|\,\sqrt{\gamma},$$4	Erasure Rate/Check	Pauli Error/Check
Dual-rail cavity	Joint-photon-splitting, parametric beamsplitter	$$K_0 = \sqrt{1-\gamma}\,I_\text{logical},\quad K_1 = |00\rangle\langle01|\,\sqrt{\gamma},\quad K_2=|00\rangle\langle10|\,\sqrt{\gamma},$$5–$$K_0 = \sqrt{1-\gamma}\,I_\text{logical},\quad K_1 = |00\rangle\langle01|\,\sqrt{\gamma},\quad K_2=|00\rangle\langle10|\,\sqrt{\gamma},$$6 ms	$$K_0 = \sqrt{1-\gamma}\,I_\text{logical},\quad K_1 = |00\rangle\langle01|\,\sqrt{\gamma},\quad K_2=|00\rangle\langle10|\,\sqrt{\gamma},$$7–$$K_0 = \sqrt{1-\gamma}\,I_\text{logical},\quad K_1 = |00\rangle\langle01|\,\sqrt{\gamma},\quad K_2=|00\rangle\langle10|\,\sqrt{\gamma},$$8	$$K_0 = \sqrt{1-\gamma}\,I_\text{logical},\quad K_1 = |00\rangle\langle01|\,\sqrt{\gamma},\quad K_2=|00\rangle\langle10|\,\sqrt{\gamma},$$9
Dual-rail transmon	Strong $|00\rangle$0, ancilla detection	$|00\rangle$1 ms	$|00\rangle$2	$|00\rangle$3
Transmon qutrit	Ancilla-assisted SWAP	$|00\rangle$4 ms	$|00\rangle$5	$|00\rangle$6
Fluxonium	Dispersive, single-resonator	$|00\rangle$7 ms	$|00\rangle$8	$|00\rangle$9

Advances in hardware design, pulse-shaping, and code integration position superconducting erasure qubits as a leading platform for scalable, fault-tolerant quantum computing based on erasure-dominated, hardware-aware error correction (Graaf et al., 2024, Liu et al., 9 Apr 2026, Huang et al., 16 Apr 2025, Dakis et al., 9 Oct 2025, Violaris et al., 5 Jan 2026, Chou et al., 2023, Koottandavida et al., 2023).