Erasure Qubit: Error Detection in QEC
- Erasure qubit is a quantum information primitive that moves qubit states out of the computational subspace upon physical errors, making them detectable as erasures.
- Dual-rail encoding in superconducting cavities and tunable transmons enables compact hardware realization and high-fidelity error detection using joint-parity measurements.
- Heralded erasure detection significantly improves QEC performance by increasing error thresholds and reducing resource overhead, facilitating scalable fault tolerance.
An erasure qubit is a quantum information primitive engineered such that its dominant error channel—a physical process such as photon loss, amplitude damping, or leakage—removes the state from the logical (computational) subspace into an orthogonal, detectable “erasure” space. The occurrence and location of these errors are signaled to the decoder in real time, enabling quantum error correction (QEC) schemes with substantially higher thresholds and lower resource overhead compared to standard qubits suffering unknown Pauli errors. This paradigm is epitomized by dual-rail encoded qubits in superconducting architectures, as realized in compact double-post cavities and tunable transmon networks, where single photon loss or transmon decay are efficiently detected and flagged as erasures, with residual dephasing or undetected errors greatly suppressed. The hierarchy of error rates, hardware-efficient detection schemes, and implications for scalable fault tolerance make erasure qubits a central object in contemporary QEC research (Koottandavida et al., 2023).
1. Logical Encoding and Physical Implementation
Dual-rail erasure qubits encode a logical qubit in exactly one excitation shared between two bosonic modes—denoted mode A and mode B in cavities, or two transmons in circuit-QED settings. The logical basis is
The codespace is the two-dimensional subspace , i.e., the single-photon or single-excitation manifold.
Physical realizations include:
- Double-post superconducting cavity: hosting two long-lived and near-degenerate modes, coupled to a single transmon ancilla for dispersive readout and joint-Wigner tomography.
- Tunable transmon dual-rail: two frequency-tunable transmons strongly coupled and readout via an ancilla transmon; gate pulses are engineered to operate exclusively within the single-excitation manifold (Levine et al., 2023, Huang et al., 16 Apr 2025).
- Metastable ion encoding: mapping the logical qubit onto metastable manifold states so that spontaneous decay channels are detected and flagged (Kang et al., 2022).
2. Error Model and Error Hierarchy
In dual-rail encoding, physical amplitude-damping (photon or transmon -type) errors map the state out of the codespace: The post-loss state is orthogonal to the codespace and is therefore unambiguously detectable via joint-parity or photon-number measurement. The resulting effective error model is an erasure channel: where denotes the erasure flag state. Crucially, erasures are heralded—the decoder knows their spacetime locations.
Experimental metrics from double-post cavities (Koottandavida et al., 2023):
- Erasure (loss) rate:
- Residual dephasing:
- Hierarchy: , i.e., loss-induced erasures are the dominant error.
This strong separation is generic in optimized dual-rail platforms, with hardware and pulse control strategies chosen to minimize residual errors within the codespace.
3. Erasure Detection Mechanisms
Detection protocols leverage the orthogonality of the erasure space:
- Dispersive ancilla measurement: Both cavity modes (annihilation operators 0, 1) are coupled to a transmon ancilla with leading-order Hamiltonian
2
with 3 for optimal parity mapping.
- Joint-parity readout (Wigner tomography): Calibrated sequences convert the joint-parity operator 4 onto the ancilla's measurement axis. Fast, high-fidelity measurements (5) distinguish in-codespace (odd parity) from erasure (even parity).
In practice, real-time erasure-flag generation uses repeated parity measurements and adaptive filters (such as hidden Markov models), achieving detection fidelities exceeding 6 and error rates compatible with next-generation QEC thresholds (Koottandavida et al., 2023, Levine et al., 2023, Hung et al., 17 Apr 2026).
4. Hardware Efficiency and Modular Scaling
The double-post cavity design presents a compact realization: two high-7 TE modes are housed in a 8 volume, with a single transmon sufficient for both erasure detection and full state tomography. The hardware implementation avoids the overhead of using separate 3D cavities or a separate ancilla per physical qubit (Koottandavida et al., 2023). This architecture supports tiling into larger arrays, offering a path toward scalable superconducting QEC with dense erasure-checking.
More generally, dual-rail encodings using transmons (Levine et al., 2023, Huang et al., 16 Apr 2025) or single qutrits (Liu et al., 9 Apr 2026) have demonstrated millisecond-scale logical 9, gate errors 0 post-erasure detection, and compatibility with standard readout and control electronics. These platforms are inherently well-matched to erasure-based QEC strategies.
5. Quantum Error Correction Thresholds and Advantages
The principal benefit of heralded erasure noise for QEC is the sizable increase in threshold and exponential error suppression:
- Surface code under erasure noise: threshold can reach 1 (code capacity) or 2 (circuit level), in stark contrast to the 3–4 under standard depolarizing noise (Koottandavida et al., 2023, Levine et al., 2023).
- Logical error scaling: For physical erasure rate 5 and code distance 6, the logical failure probability is 7 for erasures, compared to 8 for Pauli faults.
- Resource reduction: For a fixed target 9, required physical qubit overhead decreases due to both higher thresholds and steeper subthreshold scaling (Koottandavida et al., 2023, Levine et al., 2023, Huang et al., 16 Apr 2025).
Erasures, being flagged, do not propagate or mask the location of faults, significantly reducing decoder complexity and syndrome-extraction requirements. Explicit numerical studies confirm these benefits with dual-rail superconducting modules.
6. Outlook: Integration with Larger-Scale QEC and Future Applications
The realization of dual-rail erasure qubits in compact cavity modules or coupled transmon arrays—each equipped with high-fidelity, hardware-efficient erasure detection—provides a modular building block for scalable QEC architectures. Deployment of such modules in arrays, with fast classical feed-forward, enables implementation of erasure-aware outer codes (surface codes, XZZX codes, BCH-like erasure codes) with much lower resource demands. These configurations are especially favorable for quantum memory, near-term demonstration of logical gate sets, and as a testbed for adaptive erasure decoding strategies (Koottandavida et al., 2023).
Further, the erasure paradigm naturally extends to other platforms (e.g., neutral atom arrays, trapped ions with metastable shelving), and offers hardware-efficient routes to classically-limited thermodynamic erasure protocols (Neto et al., 2024), quantum-enhanced sensing (Niroula et al., 2023, Arieli et al., 12 Mar 2026), and beyond.
References:
- Koottandavida et al., "Erasure detection of a dual-rail qubit encoded in a double-post superconducting cavity" (Koottandavida et al., 2023).
- Levine et al., "Demonstrating a long-coherence dual-rail erasure qubit using tunable transmons" (Levine et al., 2023).
- Chadwick et al., "Erasure Minesweeper: exploring hybrid-erasure surface code architectures" (Chadwick et al., 30 Apr 2025).
- Mai et al., "A biased-erasure cavity qubit with hardware-efficient quantum error detection" (Mai et al., 29 Jan 2026).