Erasure Qubits in Quantum Error Correction

• Erasure qubits are quantum bits engineered to signal their errors via a known orthogonal 'erasure space', enhancing error tracking.
• They leverage dual-rail encoding and metastable systems to drastically reduce undetectable Pauli errors, improving fault-tolerance thresholds.
• Erasure-aware architectures simplify decoding and lower resource overhead, thereby optimizing error correction in quantum processors.

An erasure qubit is a physical or encoded quantum bit engineered so its dominant error mode is a heralded erasure: when the principal fault occurs, the qubit exits the computational subspace into a known orthogonal "erasure space" $|e\rangle$, and a classical flag reveals exactly which qubit and when the erasure happened. Unlike conventional Pauli noise, which induces undetectable $X$, $Y$, or $Z$ errors at unknown qubit–time locations, the erasure channel provides real-time error location and timing information. This exact knowledge enables quantum error-correcting codes to achieve substantially higher fault-tolerance thresholds and greatly reduced resource overheads compared to Pauli-noise-dominated models. Erasure-biased noise has been demonstrated in multiple architectures, notably dual-rail superconducting qubits and metastable atomic systems, and is shaping the design of early fault-tolerant quantum processors.

1. Theoretical Foundations and Noise Model

In the standard Pauli noise model, each physical qubit is subject to stochastic flips or phase errors with unknown location and time: $$\mathcal{P}(\rho) = (1-p)\,\rho + p_x X \rho X + p_y Y \rho Y + p_z Z \rho Z,$$ with $p_x + p_y + p_z = p$. In the erasure-channel model, the dominant error removes the qubit from its computational space and signals its occurrence: $$\mathcal{E}(\rho) = (1 - p_e)\rho + p_e |e\rangle\langle e|,$$ where $|e\rangle$ is an orthogonal erasure flag and $p_e$ the erasure probability. For stabilizer codes of distance $d$, the standard code can correct up to $\lfloor(d-1)/2\rfloor$ random Pauli errors, but up to $d-1$ erasures—doubling the error-correction capability at fixed code parameters (Violaris et al., 5 Jan 2026, Gu et al., 2023).

Extending to circuit models, the erasure qubit paradigm incorporates local erasure-check (EC) gates, which perform quantum non-demolition measurements to determine whether the qubit has leaked from the computational subspace after each gate or idle period. The detection outcome is flagged and used by the decoder (Gu et al., 2024).

2. Dual-Rail Encoding and Hardware Implementations

Dual-rail encoding is the canonical construction of an erasure qubit in superconducting hardware. Here, the logical qubit is encoded in the single-excitation manifold of two coupled transmons or cavity modes: $$|0_L\rangle = |01\rangle,\qquad |1_L\rangle = |10\rangle,$$ so that amplitude-damping (T$_1$) on either rail brings the state to $|00\rangle$, which is outside the logical subspace and can be unambiguously detected (Levine et al., 2023, Koottandavida et al., 2023, Huang et al., 16 Apr 2025). The effective logical channel is

$$\mathcal{E}(\rho_L) = (1-p_e)\rho_L + p_e |e\rangle\langle e|,$$

yielding a noise bias that heavily favors erasures over undetectable Pauli errors, often by ratios $\gtrsim$40:1 for gates and $\gtrsim$20:1 at idle (Levine et al., 2023).

The erasure check is typically mediated by an ancillary transmon coupled dispersively so that the ancilla’s spectrum shifts based on the total occupancy of the dual-rail system. A selective microwave pulse and high-fidelity readout then discriminates the presence of an erasure with false-positive rates $<1\%$ and false-negative rates $\sim1.5\%$, with sub-0.1\% per-check dephasing overhead (Levine et al., 2023, Koottandavida et al., 2023). Similar principles apply to dual-rail qubits based on high-Q cavities (Dakis et al., 9 Oct 2025).

In neutral-atom and trapped-ion systems, long-lived metastable states, such as $^{171}$Yb in the $^3$P$_0$ manifold or clock states in $D_{5/2}$, serve as the computational subspace. Dominant errors (spontaneous decay, photon scattering) push the system to ground or auxiliary states, which can be detected via high-sensitivity fluorescence, thus flagging erasures with efficiencies exceeding $90\%$ (Wu et al., 2022, Kang et al., 2022, Quinn et al., 2024, Zhang et al., 16 Jun 2025).

3. Quantum Error Correction Codes and Thresholds with Erasure Qubits

The knowledge of erasure locations allows decoders to operate with significantly relaxed requirements. For the surface code:

• Under i.i.d. Pauli error $p$, the effective code distance is $d_\mathrm{eff} \approx \lfloor (d+1)/2 \rfloor$, and the threshold $p^*_\text{Pauli} \approx 1\%$ (Chang et al., 2024).
• Under i.i.d. erasure rate $p_e$, the code achieves $d_\mathrm{eff} = d$ and threshold $p^*_\text{erase}\approx 4\!-\!6\%$, even with imperfect erasure detection (Chang et al., 2024, Violaris et al., 5 Jan 2026).

Logical failure rates exhibit exponential suppression with the full code distance: $p_L \sim \left(\frac{p_e}{p_e^*}\right)^d,$ contrasting with Pauli-noise scaling $p_L \sim (p/p^*)^{(d+1)/2}$. Numerical results confirm threshold enhancements by factors of 2–5 for leading QEC codes (surface, Floquet, qLDPC) in both circuit-level and phenomenological noise models (Gu et al., 2023, Gu et al., 2024, Violaris et al., 5 Jan 2026).

Hybrid architectures, where only a fraction $f_e$ of data qubits are implemented as erasure qubits and the rest remain standard, interpolate performance between all-Pauli and all-erasure models. With strategic placement (rows/columns or centered), hybrid patches can achieve effective distance and logical error rates that outperform either homogeneous limit for fixed hardware budgets, with transmon-count optimized at $f_e \approx 0.6$ for near-term chip yields (Chadwick et al., 30 Apr 2025).

Erasure-aware decoders employ minimum-weight matching on hypergraphs, with zero-weight edges for flagged erasures. This reduces decoding complexity and increases correctable error regions in $(p_e,p,q)$ space (Gu et al., 2023).

4. Experimental Demonstrations and Performance Metrics

Superconducting dual-rail qubits have demonstrated:

• Millisecond-scale T$_2$ and logical T$_1$ times (post-selected), over an order of magnitude beyond the underlying transmon $T_1$ times (Levine et al., 2023, Huang et al., 16 Apr 2025).
• Single-qubit gate errors $<10^{-4}$ with erasure probabilities per gate $\sim2\times10^{-3}$, and residual (unflagged) Pauli errors $\lesssim5\times10^{-5}$ (Levine et al., 2023).
• Two-qubit operations at the logical level (e.g., CNOT, $\sqrt{\text{iSWAP}}$) with fidelities $>96\%$ (post-selected), limited mainly by coupler-induced decoherence (Huang et al., 16 Apr 2025).
• Multi-qubit logical entanglement (logical Bell and GHZ states) and universal logical gate sets (Huang et al., 16 Apr 2025).

Metastable ion and neutral-atom erasure qubits reach:

• Erasure-conversion efficiency of $\gtrsim94\%$ for Raman scattering in $D_{5/2}$ $^{40}$Ca$^+$ (Quinn et al., 2024).
• Two-ion entanglement (SPAM-corrected) raw fidelity $98.56\%$, post-selected $99.14\%$ after discarding flagged erasures (Quinn et al., 2024).
• For $^{171}$Yb neutral atoms, erasure fractions of $56\!-\!72\%$ for idling and Clifford gates, with T$_2^*\approx 0.4$ s and T$_1>13$ s (Zhang et al., 16 Jun 2025).
• Resource and time overheads as low as $7\%$ for space–time footprint of magic-state injection with erasure qubits, for more than an order of magnitude improvement in logical error (Jacoby et al., 3 Apr 2025).

5. Erasure Conversion in Fault-Tolerant Architecture Design

The principal gain from erasure-biased noise appears in threshold elevation and overhead reduction:

• At fixed logical error rate $p_L$, the required code distance $d$ and thus number of physical qubits is reduced by factors of 2–5 in surface and Floquet codes using erasures (Kubica et al., 2022, Gu et al., 2023, Violaris et al., 5 Jan 2026).
• Magic-state injection, the leading resource bottleneck for fault-tolerant computation, is substantially improved: with as few as three erasure qubits per patch, logical injection error drops by an order of magnitude, while total space–time cost increases marginally ($\sim$10%) (Jacoby et al., 3 Apr 2025).
• Surface code and Floquet code layouts can exploit direct two-qubit Pauli measurements enabled by erasure checks, further simplifying syndrome extraction and reducing ancilla requirement (Gu et al., 2023).
• Hybrid code architectures (mixtures of erasure and standard qubits) optimize hardware budgets and chip yield for mid-scale superconducting processors (Chadwick et al., 30 Apr 2025).

Imperfect erasure checks (with finite false-positive/negative rates) retain most of the threshold and distance advantages of the ideal case, especially under "tailored Pauli" error models realized in dual-rail gates, provided the hardware is engineered for high detection fidelity and minimal check-induced dephasing (Chang et al., 2024).

6. Thermodynamics and Information-Theoretic Aspects

Erasure and information-reset processes incur thermodynamic costs governed by generalized Landauer-like bounds, with predicted minimal heats and energy expenditures for physical erasure operations. Cooperative quantum erasure using spontaneous symmetry breaking achieves reset rates near $k_\mathrm{B}T\ln2$ per bit, in microsecond timescales with $>99.9\%$ fidelity, distinct from serial algorithmic cooling (Buffoni et al., 2022). Ancilla-assisted erasure protocols can even operate below the naive Landauer limit when leveraging pure ancilla states as extra entropy sinks, consistent with generalized second-law arguments (Neto et al., 2024). For on-the-go erasure of quantum registers, optimal protocols compress classical and quantum side information to minimize energy dissipation, leveraging entanglement resources and partial knowledge of the register–system state (Meier et al., 2021).

7. Broader Applications and Future Directions

Beyond fault-tolerant quantum computation, erasure qubits improve quantum sensing and metrology by converting information loss from a quadratic to a linear decay in Fisher information, enhancing the precision of quantum clocks and Ramsey sensors at fixed error rates—the experimentally measured precision with erasure-biased noise matches the $\sqrt{1-\epsilon}$ scaling predicted by quantum estimation theory (Niroula et al., 2023).

Key open problems include optimizing erasure-check cadence, minimizing hardware cross talk and check infidelity, integrating erasure-biased encoding with bosonic and continuous-variable platforms, and developing real-time, erasure-aware decoder pipelines for large-scale devices (Violaris et al., 5 Jan 2026).

The field is advancing rapidly, with demonstrations spanning from superconducting dual-rail transmons and cavities (Huang et al., 16 Apr 2025, Koottandavida et al., 2023), to neutral-atom (Zhang et al., 16 Jun 2025, Wu et al., 2022) and trapped-ion (Quinn et al., 2024, Kang et al., 2022) architectures, and active research into resource-optimized, error-bias-exploiting codes for near-term, hardware-efficient fault tolerance.