Hardware-Efficient Erasure Qubits With Superconducting Transmon Qutrits

Abstract: Quantum error correction using erasure qubits offers higher fault-tolerant thresholds and improved scaling by converting dominant physical errors into detectable erasures. In superconducting circuits, erasure qubits can be constructed using the dual-rail approach, which, however, requires additional qubit-count overhead and tailored coupling elements. Here, we demonstrate a hardware-efficient scheme that operates transmon qutrits as erasure qubits, which is compatible with standard superconducting circuit-QED hardware. The logical states $\ket{0_\text{L}}$ and $\ket{1_\text{L}}$ are represented by the ground and second excited states, while the dominant relaxation errors can be detected via an ancilla qubit using a microwave-activated two-qutrit SWAP gate. We demonstrate a logical qubit $T_1$ lifetime exceeding $500\,μ\mathrm{s}$, post-selected with repeated mid-circuit erasure detection, which is ten times longer than the $T_1$ time of the transmon physical qubit. Coherence times beyond $300\,μ\mathrm{s}$ are achieved using dynamical decoupling. Single-qubit gate operations reach average Clifford gate infidelity on the order of $10^{-4}$. We further demonstrate dual-purposing an ancilla qubit for both erasure detection and parity checking, showing heralded generation of Bell states between erasure qubits. These results suggest that mainstream architectures of transmon qubit arrays may already be capable of implementing erasure-based QEC strategies for hardware-efficient fault-tolerant quantum computing.

• The paper introduces a novel protocol that encodes erasure qubits in the g–f states of transmon qutrits, reducing the physical qubit overhead.
• It employs ancilla-assisted mid-circuit erasure detection via a FWM-based two-qutrit SWAP gate to significantly enhance logical T1 and T2 lifetimes.
• Experimental results reveal a logical error rate of approximately 2.8×10⁻³ per cycle and improved gate fidelities, supporting scalable surface-code architectures.

Hardware-Efficient Erasure Qubits with Superconducting Transmon Qutrits

Introduction

The practical realization of quantum error correction (QEC) remains one of the primary technical challenges in scalable quantum computing. A major bottleneck is posed by the resource overheads associated with conventional QEC codes, particularly with regards to both the number and quality of physical qubits required to achieve sub-threshold logical error rates. Erasure qubits represent a promising strategy to circumvent these scaling roadblocks: by encoding logical information such that the dominant decoherence channels manifest as detectable erasures, it is possible to significantly raise the fault-tolerant noise threshold and reduce the resource overheads within QEC codes. However, most hardware demonstrations to date—especially within the superconducting circuit quantum electrodynamics (cQED) architecture—have relied on dual-rail encodings, which require multiple physical qubits and extensive ancillary hardware. This paper demonstrates a protocol for realizing erasure qubits within individual superconducting transmon qutrits, introducing a paradigm that leverages pre-existing hardware with minimal resource augmentation.

Figure 1: Device schematic and layout illustrating the erasure qubit encoded in the $\ket{g}-\ket{f}$ computational subspace of a transmon qutrit.

Erasure Qubit Realization in Transmon Qutrits

The erasure qubit is encoded into the ground ($|g\rangle$) and second excited ($|f\rangle$) states of a flux-tunable transmon, designated $|0_\text{L}\rangle = |g\rangle$ and $|1_\text{L}\rangle = |f\rangle$. In this scheme, energy relaxation processes predominantly lead to decay from $|1_\text{L}\rangle$ to the intermediate $|e\rangle$ state—a leakage event that can be detected, rather than causing a logical bit or phase-flip. This is in contrast to conventional two-level transmon encoding, where $T_1$ relaxation induces irreparable logical errors. The detection of such erasure events is accomplished with a dedicated ancilla qubit, linked to the data qubit via a microwave-activated, FWM-based two-qutrit SWAP gate that selectively maps population in the $|e\rangle$ state to the ancilla.

Figure 2: Ancilla-assisted erasure detection protocol, energy spectra, and ancilla readout discrimination for different data qubit states.

Ancilla-based erasure detection is operationalized through a parametrically activated SWAP between $|eg\rangle$ and $|g\rangle$0, which enables mid-circuit syndrome extraction. This method is tailored to standard cQED hardware, obviating the need for large hardware modifications such as those necessitated by dual-rail cavity or dual-transmon schemes. The SWAP transition is chosen to optimize selectivity and minimize hybridization of computational states with non-computational subspaces.

Logical Memory Performance and Error Budget

To assess logical qubit performance, the authors realize repeated mid-circuit erasure detection interleaved with dynamical decoupling (XY4 or spin-locking) sequences. Post-selecting on runs with zero detected erasure events, logical $|g\rangle$1 (bit-flip) lifetimes surpass 500 $|g\rangle$2s and logical $|g\rangle$3 (phase-flip) lifetimes exceed 300 $|g\rangle$4s. These values are approximately an order of magnitude higher than the corresponding physical times for the standard $|g\rangle$5–$|g\rangle$6 transmon qubit transitions, and outperform state-of-the-art dual-rail erasure qubit schemes in hardware-efficient settings.

Figure 3: Coherence measurements of the erasure qubit using repeated erasure detection and dynamical decoupling protocols.

Detailed error budget analysis reveals that the residual logical error is strongly dominated by second-order processes such as double quantum decay through $|g\rangle$7 and by rare false negatives in erasure syndrome extraction. The authors report an erasure-to-bit-flip error rate hierarchy greater than an order of magnitude: with post-selected logical error rates around $|g\rangle$8 per cycle, in close quantitative agreement with theoretical expectations derived from measured device parameters (see Supplemental Material).

Gate Fidelities and Randomized Benchmarking

Single-qubit Clifford gates for the $|g\rangle$9–$|f\rangle$0 qubit are executed via two-photon microwave-driven transitions, with DRAG pulse shaping to minimize leakage. Interleaving these gate sequences with frequent erasure checks enables effective post-selection against dominant leakage-induced errors. The protocol yields a Clifford gate infidelity of $|f\rangle$1 (physical gate infidelity $|f\rangle$2), a marked improvement over the baseline value without erasure detection ($|f\rangle$3). The error per gate is primarily limited by leakage to the $|f\rangle$4 state, and simulation benchmarks corroborate experimental results.

Figure 4: Randomized benchmarking results showing a significant reduction in Clifford gate error rates upon applying mid-circuit erasure detection.

Dual-Use Ancilla for Entanglement and Parity Checking

A key architectural advantage of the proposed scheme is the possibility of dual-purposing the ancilla qubit: it is utilized for both single-qubit erasure detection and multi-qubit parity (stabilizer) measurements, a central requirement for surface code and topological QEC implementations. The paper demonstrates a heralded Bell state generation protocol, wherein the ancilla mediates a parity measurement on two erasure qubits (each encoded in a separate transmon), yielding entangled logical states with state tomography fidelities up to $|f\rangle$5. The application of erasure detection in tandem with parity checking does not measurably reduce entanglement fidelity.

Figure 5: Parity measurement and tomography of entangled erasure qubits, demonstrating successful ancilla-mediated Bell state preparation.

Implementation and Practicality

The experiments were implemented on standard Xmon transmon hardware fabricated via conventional processes. All gate operations, including erasure-detecting SWAPs and cross-resonance CNOTs, were executed using microwave-only control, with modest qubit coherence times and without reliance on specialized device engineering (e.g., large anharmonicity or bespoke coupler layouts). The protocol thus offers near drop-in compatibility with existing mid-scale superconducting QPU architectures.

The principal limiting factors at this stage are associated with ancilla readout speed and fidelity, which can be addressed using Purcell filters and improved parametric amplifier readout hardware. Residual dephasing noise that persists after dynamical decoupling remains an open technical frontier, but does not present a fundamental scaling obstacle.

Theoretical and Architectural Implications

By embedding erasure convertibility and syndrome extraction directly into the qutrit state space of conventional transmons, this work demonstrates that the resource overheads of erasure-based QEC can be dramatically reduced: both in terms of storage qubit count (single transmon per erasure qubit) and in the multiplexing of syndrome-detecting ancillae for both erasure and stabilizer parity extraction. This is directly relevant for surface code architectures, where checking qubit layout and ancilla control complexity are dominant system engineering constraints.

Preliminary analyses suggest that the implementation of $|f\rangle$6–$|f\rangle$7 erasure qubits within a surface-code array can sustain the high fault-tolerance thresholds and accelerated logical error scaling characteristic of erasure-QEC, without incurring prohibitive hardware costs. The natural compatibility with qudit-based entangling gates and three-state readout paves the way for incorporating more general QEC codes that exploit higher-dimensional Hilbert spaces for further overhead savings.

Conclusion

This work establishes a robust framework for hardware-efficient erasure qubit realization in superconducting cQED, demonstrating longer logical memory, high single- and two-qubit gate fidelities, and practical syndrome extraction protocols using standard device architectures. The results strongly indicate that erasure-based QEC protocols can be pursued at scale in near-term transmon-based quantum processors, provided ongoing advances in readout fidelity and syndrome extraction rates. Future work will require detailed co-design of qutrit-resolved control, mid-circuit syndrome extraction, and higher-dimensional surface code layouts to approach the full performance envelope implied by the demonstrated protocols.

Reference: "Hardware-Efficient Erasure Qubits With Superconducting Transmon Qutrits" (2604.08672).