Static Phase Reconfiguration
- Static phase reconfiguration is a method that sets persistent phase states via non-volatile material switching, precomputed schedules, or quasi-static hardware updates.
- It spans diverse applications including optical metasurfaces, reconfigurable networks, distribution systems, and power converters, each interpreting 'phase' differently.
- Techniques such as laser-induced phase changes, mechanical sliding of metasurfaces, and optimized topology scheduling enhance performance by reducing control complexity and static power consumption.
Static phase reconfiguration denotes a class of techniques in which a phase-related state is set by non-volatile material switching, a precomputed schedule, a one-time planning decision, or a slow or quasi-static hardware update, rather than by dense continuous tuning. In the cited literature, the phrase spans several technically distinct objects: optical phase profiles in phase-change metasurfaces, synchronized communication phases in optical reconfigurable networks, voltage phasors and user-to-phase assignments in distribution systems, and output-wire assignments or topology modes in reconfigurable converters (Karvounis et al., 2016, Juerss et al., 26 May 2026, 1804.02080, Kerckhove et al., 8 Jul 2025, Deakin et al., 2024). The unifying feature is that the phase-related configuration is deliberately chosen to persist over a useful interval, so that switching overhead, control complexity, or static power consumption is reduced.
1. Scope and terminology
A recurring source of ambiguity is that the word “phase” does not denote the same object across the literature. In metasurfaces it usually denotes the optical phase imparted by a unit cell or pixel; in optical reconfigurable networks it denotes synchronized communication phases in a collective schedule; in distribution engineering it can denote either the voltage phasor angle or the discrete connection of single-phase users to phases $1,2,3$; and in reconfigurable converters it appears through phase-to-wire assignments or three-phase topology changes (Karvounis et al., 2016, Juerss et al., 26 May 2026, 1804.02080, Li et al., 2017).
| Domain | Meaning of “phase” | Reconfigured quantity |
|---|---|---|
| Metasurfaces and intelligent surfaces | Optical phase or phase-shift profile | Material state, geometry, or slide-position-dependent composite phase map |
| Optical reconfigurable networks | Synchronized communication phases | Sparse reusable topology states and reconfiguration schedule |
| Distribution systems | Voltage phasor or feeder phase connection | DER dispatch across switches or user phase assignment |
| Power converters | Phase-to-wire or topology association | Switch networks and selector matrices |
“Static” is likewise domain-dependent. In GST and SbS devices, the written state is non-volatile and remains stable until another optical, thermal, or electrical stimulus is applied (Karvounis et al., 2016, Liu et al., 2024). In low-voltage distribution networks, static phase reconfiguration is explicitly a multi-period planning exercise in which selected consumers are manually re-phased during routine maintenance (Kerckhove et al., 8 Jul 2025). In movable intelligent surfaces, the phase shifts themselves are static, while reconfiguration is achieved by mechanical sliding of a secondary metasurface layer (Zheng et al., 21 Nov 2025). In reconfigurable converters for unbalanced systems, the reconfiguration stage is updated on a slow “static” timescale and is not part of the high-frequency modulation loop (Deakin et al., 2024).
2. Non-volatile optical phase control in phase-change metasurfaces
In the all-dielectric GST metasurface of Karvounis et al., the reconfigurable element is a $300$ nm-thick film of GeSbTe patterned into a one-dimensional subwavelength grating with period in the range $750$–$950$ nm, slot width 0 nm, nanowire width 1, and height 2 nm. Under normal incidence with TE polarization, these gratings support high-3 (4) Mie-type resonances in reflection and transmission. The optical response is written through the complex coefficients
5
with a rapid phase variation of order 6 across resonance. Switching GST from the amorphous to the crystalline state shifts the resonance frequency by 7, approximately 8 in practice, producing
9
Rigorous-coupled wave analysis or finite-element simulation yields 0 that peaks near the original resonance; in practice, 1 can approach 2 over a 3 nm bandwidth in reflection, with similar behavior in transmission (Karvounis et al., 2016).
The switching mechanism is laser-induced and non-volatile. The amorphous4crystalline transition uses a 5 nm CW laser with spot diameter 6m and intensity 7 mW/8m9, holding GST between $300$0C and $300$1C for $300$2s until crystallization nucleates. Once set, each phase is stable at room temperature, yielding reflection contrast up to $300$3 ($300$4 dB) and transmission contrast up to $300$5 ($300$6 dB). Static phase patterns can be created either by geometric tuning, for example varying $300$7, $300$8, or the resonator diameter, or by phase-state multiplexing that locally toggles GST between amorphous and crystalline states. In reflection the imposed phase is
$300$9
The reported phase-modulation depth is 0 per resonance shift of 1 nm, while full 2 coverage is described as achievable by cascading multiple resonances or by combining geometry and state switching (Karvounis et al., 2016).
A related but electrically addressed implementation is the hybrid plasmonic–phase-change architecture of Abdollahramezani et al. Each pixel is a one-dimensional Au/GST/SiO3/Au stack with period 4 nm, Au nanoribbon width 5 nm, thickness 6 nm, GST stripe height 7 nm, and a 8 nm Au back-reflector. GST forms the dielectric gap under each Au ribbon, and its phase is switched by Joule heating. A short, high-amplitude voltage pulse of approximately 9 ns melts GST above 0C and rapid quenching re-amorphizes it, whereas a longer, lower-amplitude pulse of approximately 1s heats GST above its glass-transition/crystallization temperature of approximately 2C to nucleate and grow the crystalline phase. Thermal isolation by SiO3 ensures neighboring pixels remain below 4C, enabling individual pixel addressing (Abdollahramezani et al., 2018).
The phase modulation is governed by interference between a nearly constant non-resonant metallic reflection and a resonant Lorentzian term,
5
with 6 and 7. The GST crystallinity fraction 8 is described by a Lorentz–Lorenz effective-medium model,
9
At 0 nm, full-wave FEM/FIT simulations yield a reflected-phase sweep of nearly 1, from 2 to 3, with reflection amplitude above approximately 4 throughout. Eleven discrete states, 5, were simulated, with approximately 6 phase increment per step. The device supports a 7 nm bandwidth, approximately 8–9m, over which the phase can be reliably mapped to 0, enabling focusing, beam steering, holography, amplitude modulation, and polarization conversion (Abdollahramezani et al., 2018).
A common misconception is that static optical phase reconfiguration is equivalent to a fixed-function device. These studies show the opposite: the written state is static only between updates, while the overall platform remains rewritable and non-volatile (Karvounis et al., 2016, Abdollahramezani et al., 2018).
3. Static phase shifts with mechanical or material-state reconfigurability
The movable intelligent surface framework extends static phase design by separating phase synthesis from reconfiguration actuation. The proposed MIS consists of two transmissive metasurfaces separated by a small air gap 1: a fixed primary layer MS1 with 2 elements and static phase shifts 3, and a smaller secondary layer MS2 with 4 elements and static phase shifts 5, which slides discretely over MS1 along rows and columns. The number of slide positions is 6, where 7 and 8. At slide position 9, the equivalent phase-shift vector is
$750$0
where $750$1 is a binary selection matrix and $750$2 is a padding vector. Defining $750$3, the received signal at user $750$4 is
$750$5
The design problem jointly optimizes the static phase shifts and the slide-position selection, interpreted as beam-pattern scheduling (Zheng et al., 21 Nov 2025).
Two optimization classes are reported. For max–min rate, a penalty-assisted BCD-SCA method relaxes the binary scheduling variables, adds a penalty $750$6, and alternates over $750$7, $750$8, and $750$9. For sum rate, a Riemannian conjugate-gradient method operates on a product manifold formed by the complex-circle manifolds of $950$0 and $950$1 and the probability-simplex manifold of the scheduling matrix $950$2. Simulation results report that even a $950$3 MS2 increases min-rate by approximately $950$4–$950$5 bit/Hz over a static RIS, larger MS2 sizes such as $950$6 add up to $950$7–$950$8 bit/Hz, and element-wise MS2 mobility recovers approximately $950$9 of the gap between block-MIS and a fully dynamic RIS. At 00 dBm, the reported sum rates are approximately 01 bit/Hz for block-MIS, 02 bit/Hz for dynamic RIS, and approximately 03 bit/Hz for element-wise MIS. Reconfiguration is quasi-static, with switching latency on the order of seconds or minutes and control overhead of only 04 bits per re-pointing (Zheng et al., 21 Nov 2025).
Phase-change metasurfaces for reconfigurable image processing provide a different static mechanism. In the Sb05S06-based device of Liu et al., each nanobrick with height 07 nm, radius 08 nm, and lattice constant 09 nm supports magnetic-dipole and electric-dipole Mie resonances in the visible, observed at 10 nm and 11 nm, respectively. In the amorphous state, 12–13 and 14, yielding high-15, narrow Mie resonances and a transmission profile suitable for edge detection; in the crystalline state, 16–17 and 18, which blueshifts and broadens the resonances, lowers the 19-factor, and produces nearly angle-independent transmission. The target transfer functions are
20
Near resonance and for small absorption, the angular dependence satisfies
21
and the simulated transmission at 22 nm and 23 nm was fitted to 24, with 25 at 26. The reported modulation depth is 27, the high-28 transmission is 29 at 30 versus near 31 at 32, the numerical aperture is approximately 33, and the spatial resolution is approximately 34m at 35 nm (Liu et al., 2024).
These works show two distinct meanings of static phase reconfiguration in wave-control systems. In MIS, the phase values are static but the geometry changes; in Sb36S37 and GST metasurfaces, the geometry is fixed but the material state changes (Zheng et al., 21 Nov 2025, Liu et al., 2024).
4. Phase-matched topology states in optical reconfigurable networks
In optical reconfigurable networks, static phase reconfiguration concerns collective communication phases rather than electromagnetic phase delay. ReTri is designed for a minimal two-transceiver-per-node ORN, equivalently a ring-degree-two topology with 38 OCS ports. Assuming 39, each source block 40 is assigned a signed offset
41
which admits a unique balanced-ternary expansion
42
In phase 43, blocks with 44 are sent right, blocks with 45 are sent left, and blocks with 46 stay. This completes All-to-All in
47
synchronized phases, each served by a sparse reusable subring (Juerss et al., 26 May 2026).
The topology states are induced by residue classes
48
with bidirectional links 49 inside each 50. Each 51 is a simple ring of size 52. The paper states that no smaller subgraph can both connect the sender/receiver pairs for phase 53 and keep all future peers reachable. Reconfiguration is controlled by a binary schedule 54, where 55 means the OCS is reconfigured to the subrings 56 before phase 57, and 58 means the previous topology is reused. If the last reconfiguration occurred at phase 59, then each link is stretched by 60 in hop length, increasing propagation delay and per-link congestion (Juerss et al., 26 May 2026).
The cost model is an extended Hockney form,
61
where 62 is per-phase startup, 63 per-hop latency, 64 the per-byte transmission cost, 65 the message chunk size, 66 the maximum per-link congestion, and 67 the reconfiguration time. If ReTri reconfigures before every phase, then
68
If it never reconfigures, then
69
In practice the schedule is precomputed once from 70, 71, 72, 73, 74, and 75, and the optimal 76 is selected by evaluating 77 for 78 (Juerss et al., 26 May 2026).
In Astra-Sim/ns-3 experiments with 79 Gb/s links, 80s propagation per hop, 81s per-phase startup, and 82 swept from 83s to 84 ms, ReTri achieved up to 85 speed-up versus static All-to-All for small 86, with benefits persisting up to 87 ms for messages up to 88 MB and even 89 ms for 90 MB. It also improved reconfigurable Bruck by up to 91, with typical gains of 92–93 for small messages and 94–95 for larger messages. The central design principle is that topology optimization and communication-phase structure are co-designed rather than treated independently (Juerss et al., 26 May 2026).
A common misconception is that reconfigurable optical fabrics necessarily require per-phase topological reinstrumentation. ReTri is explicitly built around the opposite trade-off: sparse reconfiguration is used to amortize 96 across multiple phases, at the price of longer paths (Juerss et al., 26 May 2026).
5. Voltage phasors and user-phase assignment in distribution systems
One branch of the literature uses static phase reconfiguration to regulate voltage phasors before a switching action. In unbalanced distribution feeders, the linearized model developed for switch synchronization combines voltage magnitude and angle relations. For line 97,
98
and
99
where 00 and 01. Together they form the “full-phasor” linearization
02
An OPF then minimizes squared magnitude and angle differences across a target switch while keeping all voltages within 03–04 p.u. and respecting DER capacities. On modified IEEE 13-node feeders, the full phasor control case reduced the per-phase average maximum 05 from 06 p.u. in the no-control case to 07 p.u., and the maximum 08 from 09 to 10; the resulting switch flow decreased from approximately 11 p.u. to approximately 12 p.u. On the modified IEEE 37-node sequential switching case, 13 decreased from approximately 14 to 15 for the first switch and from approximately 16 to 17 for the second. Reported QP solution times were 18–19 s) on a standard PC (1804.02080).
A distinct planning-oriented use of the same phrase concerns the static re-phasing of low-voltage users. Here binary variables 20 assign single-phase user 21 to phase 22, subject to
23
The formulation can also limit the total number of switching actions through
24
Three optimization approaches are compared: an exact MINLP, an MIQP based on LinDist3Flow, and a GA. The exact MINLP supports actual imbalance metrics such as
25
while the MIQP uses proxy objectives such as 26 and 27. In a 28-user, 29-time-step case, MIQP reduced PVUR from 30 to 31 and 32 from 33 to 34, compared with 35 and 36 for the GA average. The MIQP solution times were approximately 37 min for the PVUR38 objective and approximately 39 min for the 40 objective on 41 threads, while the GA took approximately 42 min per run and the MINLP did not reach optimality within 43 h for the 44-node case. The study also reports that even 45 re-phasing, corresponding to 46, achieves approximately 47 of the maximum imbalance reduction (Kerckhove et al., 8 Jul 2025).
These two lines of work address different operational layers. The OPF-based method aligns full phasors across a switch immediately before a reconfiguration action, whereas the LV planning formulations choose a single phase-connection assignment that performs well over months to seasons (1804.02080, Kerckhove et al., 8 Jul 2025).
6. Reconfigurable power-electronic topologies and capability expansion
In reconfigurable power electronics, static phase reconfiguration is realized by changing circuit interconnections rather than continuously varying modulation parameters. One example is the automatic transformation between a three-phase 3-level cascaded H-bridge and a three-phase 2-level converter. Two topologies are presented. In Topology 1, ideal high-resistance switches reroute the midpoints; in Topology 2, a single full H-bridge replaces the separate PWM generators and the design uses two fewer ideal switches overall. A safe break-before-make sequence is specified: inhibit all PWM at 48, wait a deadtime margin, change the ideal-switch gates, wait for switch transition, then re-enable PWM on the newly selected bridge. The typical timing values given are 49–50s and 51s, with a representative total reconfiguration time of approximately 52s. In 3-level mode, the phase-to-neutral voltage is
53
with 54 V for 55 V sources; in 2-level mode,
56
The reported trade-offs are lower THD in 3-level mode, higher THD or higher switching frequency requirements in 2-level mode, and slightly higher reliability with Topology 2 because it uses fewer ideal switches (Li et al., 2017).
A second line of work concerns a low-cost reconfiguration stage at the output of balanced three-phase, multi-terminal ac/dc/ac converters for unbalanced distribution-system applications. The proposed four-wire VSC replaces fixed hard-wiring with 57 half-bridge legs and a 58 one-leg-to-four-wire selector matrix 59, where each column has exactly one 60. If 61 is the sum of all leg ratings and the leg capacities are 62 with 63, then the maximum current on wire 64 is
65
This allows leg capacity to be reassigned from one wire to another on a slow timescale, for example to support a heavily loaded phase or a large neutral current (Deakin et al., 2024).
Capability is described through a feasible injection set 66 subject to per-phase current constraints, neutral-current limits, and either standalone or interconnected dc-side power balance. In the conventional equal-leg four-wire design, the standalone active-power projection yields a regular hexagon with area
67
For an idealized fully reconfigurable converter,
68
For the proposed discrete reconfigurable converter, ignoring neutral clipping,
69
The paper reports that a conventional converter may need up to 70 greater capacity to match an idealized reconfigurable converter. For the optimally sized four-leg design 71 with 72, the required capacity increase is reported as approximately 73. Uniform 74-leg designs improve with 75, with reported standalone factors 76 for 77, 78 for 79, and 80 for 81, although the study notes diminishing marginal returns beyond 82–83 (Deakin et al., 2024).
Across converter studies, the principal trade-off is explicit: static reconfiguration increases feasible operating sets and converter utilization, but it adds selector-switch complexity, additional point-of-failure risk, and design constraints associated with neutral current and break-before-make operation (Li et al., 2017, Deakin et al., 2024).