PSC-PWM: Optimized Phase-Shifted Carrier Control

• PSC-PWM is a modulation scheme that assigns phase-shifted carrier signals to individual submodules, generating a high-quality stepped voltage output.
• Its conventional equal phase shifts minimize harmonics and ripple but require optimization under module imbalances, prompting the use of advanced numerical and AI-based techniques.
• The AI-driven real-time surrogate model significantly reduces ripple and harmonic distortion (up to 50%) with rapid inference for scalable multilevel power conversion.

Phase-Shifted Carrier Pulse-Width Modulation (PSC-PWM) is an established modulation scheme in multilevel power conversion systems, including cascaded bridge converters, modular multilevel converters (MMC), and reconfigurable battery arrays. Its defining principle is the assignment of individual carrier waveforms to each submodule, each carrier possessing an identical frequency but differentiated by a specific phase offset. This configuration enables real-time generation of the switching sequence for each submodule via comparison of the carrier with a local modulation reference, resulting in a high-quality stepped aggregate output voltage waveform. While conventional evenly-spaced phase shifts ($2\pi/N$ for $N$ modules) offer substantial harmonic suppression and current ripple reduction under balanced conditions, module imbalances necessitate carrier phase optimization to maintain output voltage quality and current uniformity.

1. Principle and Conventional Operation

In a string of $N$ series-connected submodules (half-bridges, full-bridges, or battery modules), each submodule $k$ generates its gate signal $s_k(t)$ by comparing a local modulation reference $m_k V_{\mathrm{oc},k}$ (where $V_{\mathrm{oc},k}$ is the submodule DC link or open-circuit voltage) against a high-frequency triangular or sawtooth carrier $c_k(t)$, phase-shifted by $\varphi_k$: $$\varphi_k^{(\text{conv})} = \frac{2\pi \cdot (k-1)}{N}, \quad k=1,2,\dots,N$$ The switching function is defined by: $$s_k(t) = \begin{cases} 1 & m_k V_{\mathrm{oc},k} > c_k(t + \varphi_k) \ 0 & \text{otherwise} \end{cases}$$ The aggregate output voltage across the pack (or converter string) is: $v_p(t) = \sum_{k=1}^N s_k(t) V_{\mathrm{oc},k}$ Under balanced conditions ($m_k$ and $V_{\mathrm{oc},k}$ identical for all $k$), this arrangement minimizes low-order harmonics and achieves a near-ideal staircase waveform, with ripple current suppressed by a factor of $1/N^2$.

2. Mathematical Formulation and Harmonic Analysis

2.1 Carrier Construction and Switching Function

Carriers for each module are defined: $$c_k(t) = \text{tri}(2\pi f_{\text{sw}} \, t + \varphi_k)$$ where $f_{\text{sw}}$ is the switching frequency and $\varphi_k$ the carrier phase offset.

The periodic switching function $s_k(t)$ allows a Fourier series expansion: $$s_k(t) = \frac{1}{2}a_{0k} + \sum_{n=1}^\infty [a_{nk} \cos(n\omega t + \varphi_k)]$$ with coefficients: $$a_{0k} = 2 m_k, \qquad a_{nk} = \frac{2}{n\pi} \sin(n\pi m_k), \qquad b_{nk} = 0$$

2.2 Ripple Current and Harmonic Distortion

The converter’s ripple current $\Delta i_p(t)$, derived from the inductor equation $L \frac{d i_p}{dt} = v_p - v_o$, is: $$\Delta i_p(t) = \sum_{k=1}^N \sum_{n=1}^{\infty} \left( \frac{2}{L \omega n^2 \pi} \sin(n\pi m_k) \sin(n\omega t + n \varphi_k) \right) + i_0$$

The amplitude of the $n$-th harmonic is: $$A_n = \sqrt{ \left[ \sum_k \frac{2V_{\mathrm{oc}}}{L\omega n^2 \pi} \sin(n \pi m_k) \sin(n\varphi_k) \right]^2 + \left[ \sum_k \frac{2V_{\mathrm{oc}}}{L\omega n^2 \pi} \sin(n\pi m_k) \cos(n\varphi_k) \right]^2 }$$

Weighted total harmonic distortion (WTHD), emphasizing lower harmonics, is given by: $$\mathrm{WTHD}_{\mathrm{dc}} = \frac{\sqrt{ \sum_{n=1}^\infty w_n A_n^2 }}{V_{\mathrm{dc}}}$$ where $w_n$ is a designer-chosen harmonic weighting.

3. Impact of Module Imbalances and Optimization Requirements

When the modulation indices $m_k$ (and/or $V_{\mathrm{oc},k}$) are nonuniform—due to balancing objectives, faults, or reconfiguration—using uniform phase shifts $\varphi_k = 2\pi (k-1)/N$ causes pulse width nonuniformity. The consequence is incomplete vectorial harmonic cancellation across modules, yielding increased ripple current ($\Delta i_p$), enhanced low-order harmonics in $v_p(t)$, and degraded $\mathrm{WTHD}_{\mathrm{dc}}$. As these harmonic phasors sum, optimal phase angles $\varphi_k^*$ that minimize distortion must be computed as functions of the entire $m$ vector.

Optimization of phases for arbitrary $m$ is nontrivial. Sensitivity analysis via linearization: $$\delta A_n \approx \sum_k \delta\varphi_k \frac{\partial A_n}{\partial \varphi_k}$$ highlights the pronounced impact of phase selection on harmonic amplitudes, motivating precise numerical or data-driven optimization.

4. Optimization Problem Formulation

The phase-shift optimization problem seeks decision variables: $$\varphi = [\varphi_1, \varphi_2, \dots, \varphi_{N-1}], \quad \varphi_k \in [0,2\pi)$$ with one reference phase (typically $\varphi_N=0$) to avoid redundancy.

Objective function (cost): $$J(\varphi, m) = w_1 \Delta i_p(\varphi, m) + w_2 \mathrm{WTHD}_{\mathrm{dc}}(\varphi, m)$$ subject to constraints: $$\varphi_k \in [0,2\pi), \quad \text{optionally}\; \varphi_1 \leq \varphi_2 \leq \dots \leq \varphi_{N-1}$$

Offline methods (genetic algorithms, exhaustive search) can compute optimal sets $\varphi_k^*$ but are incompatible with real-time inference due to prohibitive runtimes (order $10^{1}$–$10^{4}$ s per operating point).

5. AI-Based Real-Time Phase Prediction

A supervised neural network surrogate is constructed to emulate this instantaneous optimization. The architecture is fully connected, with seven layers and exponentially decaying neuron counts per layer. For $N$ modules:

• Input: Sorted modulation indices $[m_{(1)}, \dots, m_{(N)}]$ or their complement $1-m_k$
• Output: Predicted optimal phase-shifts $[\varphi_1, \dots, \varphi_{N-1}]$
• Activation: $\tanh$ (hidden layers), linear (output)
• Regularization: L2 ($\lambda=10^{-4}$)
• Training: Adam optimizer, learning rate $10^{-3}$, batch size $512$, early stopping ($50$ epochs)

Training data are generated by random $m$ vectors ($[0,0.5]$), label phases via GA optimizer (300 generations, discretization $\pi/5$). The loss is mean absolute error: $$L = \frac{1}{N-1} \sum_{k=1}^{N-1} |\hat{\varphi}_k - \varphi_k^*|$$ A single training session per base count $N_b$ suffices.

6. Scaling and Practical Implementation

To accommodate larger system sizes $M = N_b \cdot z$:

• Partition $m$ into $z$ sub-vectors $m^{(z)}$ of size $N_b$
• Apply trained $N_b$-network to each $m^{(z)}$ to obtain $\varphi^{(z)}$
• Apply offset: $$\Delta \varphi_z = \frac{2\pi(z-1)}{M}, \quad z=1,\dots,\frac{M}{N_b}$$
• Assemble the overall $\varphi$ by concatenating the offset phases

This scaling yields $\sim 90\,\%$ of the performance of full retraining and eliminates retraining overhead. Carrier mapping between triangular and sawtooth alignments is handled via: $$\varphi_i^{\text{saw}} = \text{wrap}_{2\pi} \left( \varphi_i^{\text{tri}} \pm \frac{\pi}{2} m_i \right)$$

Embedded implementation proceeds as follows:

1. If all $m_k$ equal: use conventional $\varphi_k = 2\pi (k-1)/N$
2. Else if $N$ divides $N_b \cdot z$: partition and use scaling offset strategy
3. Else: predict using NN for sorted $m$
4. For sawtooth carriers: apply phase correction
5. Generate carriers $c_k(t)$
6. For $t\in[0,T_s)$, set $s_k=1$ iff $m_kV_{\mathrm{oc},k}>c_k(t)$; update gate signals
7. Iterate each PWM period

7. Empirical Assessment and Performance Metrics

In large-scale evaluation (10,000 random $m$ points, 4 modules):

• 96.88 % of neural network predictions fall within 1 % of global GA optimum cost
• 53.5 % of cases outperformed conventional equally-spaced PSC-PWM

Average reductions documented:

• Current ripple ($\Delta i_{\text{ripple}}$): $\sim 50\,\%$
• Weighted total harmonic distortion (WTHD): $\sim 50\,\%$

Scaling to 8 modules via partitioning maintains $\sim 40\,\%$ ripple and distortion reductions and achieves $\sim 90\,\%$ of full retrain performance. Experimental validation on a 4-string reconfigurable battery bench (including fault scenarios) confirms that the method delivers up to 50 % reduction in ripple current and WTHD, with simulation and experiment agreeing within a few percent.

Inference time is improved by factors of 100,000–500,000 compared to offline optimizers (e.g., GA), enabling genuine real-time application within embedded controllers.

8. Context, Significance, and Implications

PSC-PWM remains an effective scheduling algorithm for multilevel power conversion architectures. Recent advances in neural surrogate optimization have overcome the computational infeasibility associated with real-time phase-shift optimization in the presence of modulation imbalance. The described AI-driven method avoids reliance on lookup tables, numerical solvers, or complex controller tuning, instead requiring only a single (re)training session per module base count and offering full scalability for larger systems. This enables a direct reduction in passive filter requirements, improves output quality and efficiency, and supports advanced converter topologies such as reconfigurable batteries and fault-tolerant MMCs.

A plausible implication is widespread practical adoption of phase-optimized PSC-PWM in flexible power electronics, with neural network surrogates as embedded controllers for high-rate, large-scale systems. The scaling strategy facilitates rapid adaptation to system resizing, and empirical evidence corroborates the substantial reduction of ripple and distortion under real-time, on-the-fly operation.