Source Retention Loss in MIFIS FeFETs

• Source Retention Loss (SRL) is the time-dependent decay of the programmed erase state in MIFIS-FeFETs caused by gate-injected charge de-trapping, leading to a memory window reduction of up to 50% over 10 years.
• The phenomenon is quantitatively characterized by measurable threshold voltage shifts (e.g., approximately -2.9 V per 3.4 nm G.IL) and trapped charge ratios (around 170% of P_S) that underline its impact on device performance.
• Mitigation strategies focus on optimizing gate-interlayer materials and thicknesses to elevate energy barriers for charge detrapping, thereby enhancing long-term retention in nonvolatile memory applications.

Source Retention Loss (SRL) in ferroelectric field-effect transistors (FeFETs) employing a metal-insulator-ferroelectric-insulator-semiconductor (MIFIS) structure refers to the phenomenon where the programmed erase state (high threshold voltage, $V_{th}$) degrades over time due to loss of gate-injected charge. This process manifests as a progressive downward shift of the erase threshold voltage $V_{th,ERS}$ during stand-by, leading to a significant reduction in the memory window—often by approximately 50% over a 10-year extrapolated retention period. The instability of the erase arm is particularly prominent, severely challenging long-term nonvolatile storage applications in advanced 3D FE NAND architectures (Han et al., 17 Oct 2025).

1. Definition and Manifestation of SRL in MIFIS-FeFETs

Source Retention Loss (SRL) is defined as the time-dependent reduction of the programmed erase state in MIFIS FeFET devices, specifically observed as a negative drift in the erase threshold voltage $V_{th,ERS}$ over retention periods spanning $10^4$–$10^5$ s and extrapolated up to 10 years. In practice, this retention loss can reduce the original memory window by up to 50%, with the erase arm exhibiting the greatest instability. This characteristic distinguishes SRL from general retention degradation seen in conventional ferroelectric structures and establishes it as a key reliability challenge in MIFIS-based nonvolatile memory (Han et al., 17 Oct 2025).

2. Physical Mechanisms: Gate-Injected Charge De-Trapping vs. Ferroelectric Depolarization

In conventional MFIS devices, retention loss is predominantly attributed to the depolarization field $E_{dep} = P_S / \epsilon_{FE}$, causing relaxation of the ferroelectric polarization ($P_S$). However, in MIFIS-FeFETs, Han et al. demonstrated that SRL is not governed by ferroelectric depolarization but instead by the de-trapping of gate-injected charges ($Q_G$). During retention ($V_g = 0$ V), the internal bias divides into a negative voltage ($V_{FE} \approx -2.3$ V for $V_{th,ERS}$0 nm) supporting $V_{th,ERS}$1, and a positive voltage ($V_{th,ERS}$2 V) across the gate-side interlayer (G.IL), which promotes de-trapping of $V_{th,ERS}$3 either back to the metal gate (Path I) or toward the channel/interlayer (Path II).

No significant decay of $V_{th,ERS}$4 is observed in gate-current ($V_{th,ERS}$5) measurements during a read sweep ($V_{th,ERS}$6 V), indicating that ferroelectric depolarization is negligible for retention loss physics in this context. Instead, all observable $V_{th,ERS}$7 shifts over retention are quantitatively accounted for by $V_{th,ERS}$8 de-trapping. This decouples charge loss mechanisms from ferroelectric relaxation in these systems (Han et al., 17 Oct 2025).

3. Quantitative Relationships and Charge Extraction

SRL is characterized by distinctive charge ratios and quantitative behaviors:

• The total displacement charge at $V_{th,ERS}$9 is expressed as $V_{th,ERS}$0, with $V_{th,ERS}$1 obtained from $V_{th,ERS}$2–$V_{th,ERS}$3 loops (e.g., $V_{th,ERS}$4) and $V_{th,ERS}$5 (e.g., $V_{th,ERS}$6 MV/cm) extracted from polarization loop fits.
• The electric field in the gate-side interlayer, $V_{th,ERS}$7, derives from the slope of $V_{th,ERS}$8 versus $V_{th,ERS}$9-EOT: $10^4$0 V/nm, resulting in $10^4$1 MV/cm.
• Gauss’s law gives the trapped charge fractions:

$10^4$2

• For $10^4$3 nm, it is determined experimentally that $10^4$4 and $10^4$5, independent of thickness.
• The shift in threshold voltage due to loss of trapped charge is given by:

$10^4$6

For SiO$10^4$7 G.IL ($10^4$8), $10^4$9 over retention results in $10^5$0 V per 3.4 nm G.IL (Han et al., 17 Oct 2025).

Parameter	Experimental Value	Formula/Notes
$10^5$1	$10^5$2	From $10^5$3–$10^5$4 loops on FeCAP
$10^5$5	$10^5$6 (170%)	Independent of $10^5$7
$10^5$8	$10^5$9 (130%)	Independent of $E_{dep} = P_S / \epsilon_{FE}$0
$E_{dep} = P_S / \epsilon_{FE}$1	$E_{dep} = P_S / \epsilon_{FE}$2 MV/cm	Slope of $E_{dep} = P_S / \epsilon_{FE}$3 vs. $E_{dep} = P_S / \epsilon_{FE}$4

4. Band Structure, Trap Levels, and Detrapping Pathways

The energy-band diagram under retention ($E_{dep} = P_S / \epsilon_{FE}$5) for MIFIS-FeFETs is: TiN Metal – SiO$E_{dep} = P_S / \epsilon_{FE}$6 G.IL – Hf$E_{dep} = P_S / \epsilon_{FE}$7Zr$E_{dep} = P_S / \epsilon_{FE}$8O$E_{dep} = P_S / \epsilon_{FE}$9 FE – SiO$P_S$0 C.IL – Si.

A principal deep trap level, $P_S$1, is positioned approximately 3.0 eV below the SiO$P_S$2 conduction band edge, providing a reservoir for $P_S$3. The two relevant charge loss pathways are:

• Path I (to metal): $P_S$4
• Path II (to channel): $P_S$5

As $P_S$6 increases, $P_S$7 moves closer to the Si conduction band (due to $P_S$8 becoming more negative), decreasing $P_S$9 (facilitating Path II) but increasing $Q_G$0 (hampering Path I). The dominant detrapping path thus transitions from Path I to Path II with increasing $Q_G$1 thickness (Han et al., 17 Oct 2025).

5. Dependence of Retention Time on Interlayer Thickness and Detrapping Kinetics

Retention time exhibits a non-monotonic dependence on the $Q_G$2 thickness ($Q_G$3). Charge emission (detrapping) is modeled using a non-radiative multiphonon (NMP) emission framework:

$Q_G$4

For $Q_G$5 eV, $Q_G$6 eV, $Q_G$7 s:

• For thin $Q_G$8 ($Q_G$9–$V_g = 0$0 nm), Path I dominates (detrapping times $V_g = 0$1–$V_g = 0$2 s), inducing poor retention.
• For thick $V_g = 0$3 ($V_g = 0$4 nm), Path II prevails ($V_g = 0$5–$V_g = 0$6 s), shifting the bias-dependence.

Thus, both excessively thin and thick $V_g = 0$7 layers degrade retention: if too thin, rapid tunneling through Path I; if too thick, energy band alignment enables efficient Path II detrapping, each leading to suboptimal retention characteristics (Han et al., 17 Oct 2025).

6. Material and Device Design Strategies for SRL Mitigation

Optimizing MIFIS-FeFETs for minimal SRL involves coordinated strategies targeting both charge injection and detrapping pathways, as follows:

• Gate-interlayer (G.IL) engineering: Adoption of materials with larger bandgap and higher conduction-band offset (e.g., SiN or Al$V_g = 0$8O$V_g = 0$9/HfO$V_{FE} \approx -2.3$0/Al$V_{FE} \approx -2.3$1O$V_{FE} \approx -2.3$2 stacks) elevates energy barriers for both detrapping paths.
• Physical thickness and dielectric constant: Employing a physically thicker but low-$V_{FE} \approx -2.3$3 G.IL maximizes tunneling distance (suppressing Path I) while minimizing $V_{FE} \approx -2.3$4 to preserve a large memory window.
• Ferroelectric layer tuning: Moderate $V_{FE} \approx -2.3$5 is essential—adequate for a large memory window yet avoiding excessive $V_{FE} \approx -2.3$6 injection that amplifies SRL risk.
• Channel interlayer/Silicon interface tailoring: Adjustments such as post-anneal nitridation help modulate $V_{FE} \approx -2.3$7, impeding Path II detrapping.

These design principles serve to maximize both $V_{FE} \approx -2.3$8 and $V_{FE} \approx -2.3$9, thus suppressing both detrapping paths and restoring 10-year retention capability while supporting memory window requirements suitable for 3D FE-NAND (Han et al., 17 Oct 2025).