Silicon Diode Selector: MIS vs. MSM

• Silicon diode selector is a semiconductor device engineered for high nonlinearity to suppress sneak-path leakage in RRAM crossbar arrays.
• The MIS structure uses an Al/Si₃N₄/p-Si stack for self-rectifying operation, while the MSM selector employs a back-to-back Schottky configuration with a low-doped a-Si layer.
• Both selectors offer practical trade-offs in operating voltage, endurance, and array scalability, making them essential for advanced nonvolatile memory integration.

A silicon diode selector is a semiconductor structure engineered to provide highly nonlinear current–voltage (I–V) characteristics for the suppression of leakage currents (“sneak-paths”) in high-density resistive random access memory (RRAM) crossbar arrays. By acting as a non-volatile memory (NVM) selector device, the silicon diode ensures that only targeted memory cells are addressed during write and read operations while minimizing crosstalk and current spreading. Two technologically prominent architectures are the self-rectifying Al/Si₃N₄/p-Si metal–insulator–semiconductor (MIS) selector and the amorphous-silicon (a-Si) back-to-back Schottky diode (metal–semiconductor–metal, MSM) selector. Both aim to combine scalably low leakage, high nonlinearity, large endurance, and compatibility with back-end-of-line (BEOL) integration.

1. Device Architectures and Materials

The silicon diode selector can manifest as either an intrinsic part of the resistive switching cell or as a discrete selector stack:

• MIS Self-Rectifying Selector (Al/Si₃N₄/p-Si):
  • Substrate: (100)-oriented p-type silicon wafer, doping $\sim10^{15}$–$10^{16}$ cm⁻³.
  • Insulator: 8 nm Si₃N₄ via low-pressure chemical vapor deposition (LPCVD) at 750 °C with dichlorosilane and ammonia precursors.
  • Top electrode: 100 nm Al, 100 μm diameter via RF sputtering.
  • Reference device: Identical Si₃N₄ thickness stacked on a Ti bottom electrode for direct comparison.
• MSM Back-to-Back Schottky Selector:
  • Structure: Thin ($\sim$10–14 nm) low-doped a-Si layer sandwiched between two metals, forming Schottky junctions at both interfaces.
  • Electrodes: Commonly Ti (work function $\sim$4.3 eV, $\phi_b\sim0.79$ eV) and Ni ($\sim$5.0 eV, $\phi_b\sim0.86$ eV).
  • Doping: Intentionally low $N_\mathrm{D}\sim10^{13}$–$10^{14}$ cm⁻³ to suppress tunneling and maintain thermionic emission as the dominant transport mechanism.
  • Fabrication: Plasma-enhanced CVD for the a-Si layer; crossbar areas from 300 nm to 10 μm lateral size.

2. Conduction Mechanisms and Governing Models

The fundamental operating principle is current rectification and nonlinear conduction to block leakage during unselected half-bias conditions:

• MIS Selector:
  • The Si₃N₄/p-Si interface forms a large conduction and valence band offset ($\Delta E_C\sim2.1$ eV, $\Delta E_V\sim3.1$ eV), creating a Schottky-like barrier.
  • Under negative Al bias, electrons inject from p-Si into Si₃N₄ defects and reach the Al electrode—enabling both switching and readout (“diode-on”).
  • Positive bias exposes the Schottky barrier in reverse: leakage current is markedly suppressed (“diode-off”).
  • Current–voltage is described by Schottky thermionic emission $I=I_0[\exp(qV/nkT)-1]$ and trap-assisted space-charge-limited current (SCLC) with Poole–Frenkel correction ($J=C\,E\exp[-(\phi_t-\beta\sqrt{E})/kT]$).
• MSM Selector:
  • Each metal/a-Si contact forms a Schottky barrier; under bias, one junction is forward- and the other is reverse-biased.
  • At intermediate biases, thermionic emission dominates, described by

  $$J_{MSM}(V)\approx J_S\tanh\left(\frac{qV}{2nkT}\right),$$

  further refined as

  $$J_{MSM}=J_S\sinh\left(\frac{qV}{2kT}\right)\exp\left(\frac{qV}{2kT}\right)\exp\left(-\frac{qV}{nkT}\right).$$ - Nonlinearity ratio is defined as $NL=I(V_{read})/I(V_{half\text{-}read})$, with targets $NL>5\times10^5$.

3. Electrical Characteristics and Performance Metrics

Performance measures of a silicon diode selector center on nonlinearity, leakage suppression, endurance, retention, speed, and scalability:

Parameter	MIS Selector (Al/Si₃N₄/p-Si)	MSM Selector (a-Si MSM)
Forming/Set Voltage	±15 V	$<2$ V for $J_{read}\sim1$ MA/cm²
LRS Current (1 V)	∼13 μA	Adjustable ($\sim$1 MA/cm² @ 1.3–1.6 V)
HRS Current (1 V)	∼30 pA	Tunable
Nonlinearity Ratio	$\sim10^3$ at 1 V	$>5\times10^5$ at half-read
Endurance	DC sweeps, no cycles reported	$>10^8$ pulses, $>10^3$ s DC stress
Read-Margin (CBA array)	>50% for up to $17\times17$	High, array-scale dependent
Switching Speed	—	$<60$ ns

• MIS Selector: Demonstrates $\sim10^3$ rectification, $I_\mathrm{LRS}/I_\mathrm{HRS}\sim4\times10^5$, low standby leakage for one bias polarity, passive array read margin above 50% up to $17\times17$ arrays.

• MSM Selector: Achieves $NL>5\times10^5$, sub-2 V operation, response time below 60 ns, endurance exceeding $10^8$ cycles, and robust DC stress tolerance.

4. Key Design Considerations and Scaling Strategies

Achieving optimal selector behavior necessitates careful tuning of material parameters:

• MIS Selector:

  • Lowering Si₃N₄ thickness from 8 nm can decrease required set/reset voltages.
  • Engineering the Si₃N₄/p-Si interface (doping, treatment) can modulate the Schottky barrier height and ideality factor.
  • Implementation as a self-rectifying cell enables lower area than 1D1R (one diode, one resistor) or 1T1R (one transistor, one resistor) schemes.
• MSM Selector:
  • Metal work function ($\Phi_m$) directly controls the Schottky barrier ($\phi_B$), impacting both leakage and nonlinearity.
  • a-Si thickness should be 10–14 nm: thinner risks pinholes/tunneling, thicker increases series resistance.
  • Doping $N_D$ must be minimized ($<10^{14}$ cm⁻³) to retain purely thermionic emission and suppress tunneling.
  • Ensure RC-limited switching by minimizing layout capacitance ($<$1 fF) and employing 50 Ω impedance matching.
• General Integration:
  • Both selectors are compatible with BEOL processing (LPCVD/PECVD).
  • MSM selectors especially support array scaling above $64\times64$ due to higher nonlinearity, but nonlinearity of the MIS cell ($n_{\text{on/off}}\sim10^2$–$10^3$) may require further optimization for ultra-large arrays.

5. Comparative Advantages, Limitations, and Application Domains

Advantages and constraints for each selector architecture are as follows:

• MIS Selector Advantages:
  • True 1S1R operation in a single two-terminal stack.
  • Suppressed sneak-path current and large read margin in dense passive arrays (proven up to $17\times17$).
  • CMOS-compatible materials and process flows.
• MIS Selector Limitations:
  • High forming and set/reset voltages ($\sim\pm15$ V).
  • Moderate nonlinearity and incomplete demonstration of commercial-class endurance and retention.
• MSM Selector Advantages:
  • High nonlinearity ratio ($>5\times10^5$), low operating voltage ($<$2 V), high speed ($<$60 ns).
  • Demonstrated endurance ($>10^8$ cycles) and stability under DC stress.
  • General design guidelines facilitate parameter optimization (metal choice, thickness, doping).
• Application Domains:
  • Both selectors are tailored for high-density, passive RRAM arrays requiring suppression of sneak-currents without incurring significant area or fabrication complexity.
  • The self-rectifying MIS structure is suitable for co-integrated RRAM memory with low standby power, whereas MSM selectors are preferable when extreme nonlinearity and endurance are paramount (e.g., large-scale crossbar integration).

6. Reliability, Endurance, and Commercial Prospects

Both architectures show promise for selector-free memory arrays but face different validation stages:

• MIS Selector:
  • Stable DC switching is observed over multiple sweeps; explicit endurance (cycle count) and long-term retention ($>10^4$ s) data are absent.
  • The large read margin and low HRS leakage suggest viability under typical RRAM stress but full commercial qualification demands demonstration of $>10^5$ cycles and $>10$ years retention.
• MSM Selector:
  • Endurance exceeds $10^8$ switching pulses, and leakage shows minimal drift under $10^3$ s DC stress.
  • Fast response and stability permit integration in high-speed, large-array NVMs.

A plausible implication is that MSM selectors currently satisfy more of the standard industrial reliability criteria, while MIS selectors offer an area- and process-efficient alternative pending further endurance optimization.

7. Outlook and Research Directions

Progress in silicon diode selector technology continues to focus on:

• Reducing operating voltages (via thickness scaling, interfacial engineering).
• Enhancing nonlinearity without compromising read current, for deployment in increasingly large arrays.
• Demonstrating industrially-relevant endurance, retention, and array-level error rates.
• Developing robust BEOL integration schemes aligned with advanced CMOS nodes.

Selector research is central to enabling ultra-dense, crossbar-based RRAM and future high-performance, energy-efficient NVMs, as reflected in ongoing investigations into both self-rectifying MIS and a-Si MSM approaches (Yun et al., 2016, Hsieh et al., 2016).