Sargantana: RISC-V CPU with Vector & HUB Adder

• Sargantana is an open-source, Linux-capable, 64-bit RISC-V CPU design based on the RV64G ISA that integrates vector/SIMD support and custom extensibility.
• It features a tailored floating-point HUB adder that reduces area by 25% and pipeline latency by one cycle while preserving IEEE-754 precision via a novel truncation method.
• The architecture is tightly integrated into multicore systems with an advanced OpenPiton-based tile design and a coherent memory hierarchy optimized for HPC workloads.

Searching arXiv for papers on Sargantana to ground the article in published work. arXiv Search Query: all:"Sargantana" Sargantana is a Linux-capable 64-bit RISC-V CPU described in two complementary arXiv publications: one presents it as the compute core used in REPTILES, an OpenPiton-based multicore for HPC-oriented workloads, and the other presents a tailored floating-point HUB adder implemented in the processor (Oliete-Escuín et al., 6 May 2026, Bandera et al., 2024). Across these descriptions, Sargantana is characterized as an open-source, in-order design centered on the RV64G ISA, with vector or SIMD support, extensibility via custom instructions, and explicit attention to area, latency, and multicore scalability.

1. Architectural identity and published configurations

The published record presents Sargantana in two closely related configurations. In the REPTILES work, it is a Linux-capable, single-issue, in-order RV64G processor enhanced with the RISC-V Vector Extension v1.0 and several custom features for HPC workloads. In the HUB-adder work, it is a 64-bit, in-order, Linux-capable RISC-V CPU implementing the RV64G base ISA, augmented with a SIMD unit and support for the RVV-0.7.1 vector extension (Oliete-Escuín et al., 6 May 2026, Bandera et al., 2024).

Aspect	REPTILES description	HUB-adder description
Execution model	Single-issue, in-order	In-order
Vector/SIMD support	RVV v1.0 integer extension	SIMD unit and RVV-0.7.1
Pipeline description	Five-stage tile pipeline	7-stage integer pipeline
Data cache emphasis	16 KB HPDcache interface	Non-blocking 32 KB L1 data cache
Platform role	Core in OpenPiton multicore	Host processor for tailored FPU adder

The REPTILES paper describes a classic five-stage tile pipeline: IF, ID, EX, MEM, and WB. The HUB-adder paper describes a 7-stage integer pipeline with Fetch, Decode, Register Rename, Execution, and Write-Back stages, together with register renaming, out-of-order write-back, and a non-blocking L1 data cache. This suggests a documented evolution in implementation emphasis: the later REPTILES presentation foregrounds OpenPiton integration, RVV v1.0, and HPC-specific memory-system refinements, whereas the earlier HUB-adder presentation foregrounds the scalar/FPU pipeline and custom arithmetic support.

2. Core microarchitecture and ISA support

In the REPTILES configuration, each Sargantana tile implements a five-stage datapath in which IF fetches from a 16 KB L1 i-cache via the NoC, ID decodes RV64G and Vector instructions and reads integer/vector register files, EX dispatches to ALU, multiplier, FPU, or vector unit, MEM accesses data caches or the HPDcache, and WB commits integer, FP, or vector results. The integer ALU supports RV64I, M, and A for 64-bit arithmetic, logic, shifts, and atomics; the FPU supports IEEE-754 single and double precision through RV64F/D; and the vector unit supports RVV v1.0 integer vectors with $\mathrm{LMUL}=1$ only and 8-, 16-, 32-, and 64-bit element widths (Oliete-Escuín et al., 6 May 2026).

The same source states that scalar vector FP is not yet implemented. Supported ISA extensions are listed as RV64I, M, A, F, D, together with the RVV 1.0 integer extension, the Debug extension Sdext, and Sscofpmf for reading performance counters via Linux perf. The core also incorporates three new architectural features: an RVV 1.0 upgrade with vector-config renaming, a high-performance data cache interface, and simulation checkpointing in Verilator. The vector-config renaming mechanism treats instructions such as vsetvl as ordinary register writes, eliminating pipeline bubbles. The HPDcache interface is a second D-cache port specialized for streaming and HPC patterns, and the paper reports reduced access latency by up to 20% in microbenchmarks. Simulation checkpointing allows users to save and restore RTL state mid-simulation.

The REPTILES paper gives typical performance metrics of $\mathrm{IPC} \approx 0.9$ on integer benchmarks, with

$$\mathrm{IPC} = \frac{\mathrm{instructions\_retired}}{\mathrm{cycles\_elapsed}},$$

and

$\mathrm{CPI} = \frac{1}{\mathrm{IPC}}.$

It also reports vector throughput of approximately $4\times$ a single-lane integer ALU for 64-bit element operations. In the HUB-adder paper, the baseline Sargantana FPU is described as fully pipelined, executing a floating-point addition in six stages and supporting IEEE-754 round-to-nearest, guard/round/sticky bits, and denormals (Bandera et al., 2024).

3. Floating-point subsystem and the HUB adder

A distinct line of work on Sargantana introduces a tailored floating-point HUB adder. The HUB format is described as a “half-unit-bias” real-number representation that preserves IEEE-754 precision and accuracy while replacing the conventional round-to-nearest-even sequence with a single truncation. For a normalized floating-point number

$x = (S_x, M_x, E_x),$

the sign bit $S_x$ and exponent $E_x$ are the same as in IEEE-754, while the significand $M_x$ satisfies

$1 < M_x < 2.$

The paper gives two complementary forms for the significand (Bandera et al., 2024):

• Representative form:

$\mathrm{IPC} \approx 0.9$0

• Operational form:

$\mathrm{IPC} \approx 0.9$1

The implicit trailing 1 encodes the $\mathrm{IPC} \approx 0.9$2 bias, so truncation implements nearest-neighbor rounding without a dedicated rounding circuit, guard bit, or sticky-bit calculation. Starting from Sargantana’s original six-stage IEEE-754 adder, the HUB version reduces the pipeline to five stages: operand fetch and exponent-difference calculation; alignment and optional two’s-complement formation for subtraction; significand addition or subtraction with overflow correction; leading-zero detection; and barrel-shifter normalization with final write-back. The paper states that no separate rounding stage is required because the result already carries the $\mathrm{IPC} \approx 0.9$3 bias in its LSB.

The synthesis results are explicit. The conventional IEEE-754 FPU adder area is 3110 $\mathrm{IPC} \approx 0.9$4, whereas the HUB adder area is 2332 $\mathrm{IPC} \approx 0.9$5, giving

$\mathrm{IPC} \approx 0.9$6

that is, a 25% area reduction. Pipeline depth is reduced from 6 to 5, lowering per-addition latency by one cycle, approximately 17%. The maximum clock frequency remains at or above 1 GHz, and dynamic power is described as reduced roughly in proportion to area and cycle count, approximately 20–25%, because the removed rounding stage no longer switches.

The same paper also states the limitations of this arithmetic path. The HUB format only supports normalized results; subnormals are not handled. Only round-to-nearest is directly supported by truncation; other rounding modes would require additional logic. Tie-to-even semantics are not enforced. The current integration covers only the add/subtract datapath, while multiply, divide, square-root, and full IEEE exception/status handling remain future work.

4. Memory hierarchy, cache system, and interconnect

In REPTILES, Sargantana is not deployed as an isolated core; it plugs directly into OpenPiton’s tile and cache hierarchy. Each tile consists of a 16 KB private L1 I-cache that is direct-mapped, a 16 KB private HPDcache that is 4-way, a 32 KB private L1.5 cache that is 8-way with 64 B lines, and a 64 KB shared L2 cache that is 16-way with 64 B lines and uses directory-based MESI coherence (Oliete-Escuín et al., 6 May 2026).

The cache parameters are also specified. All private levels have 64 MSHRs, fully pipelined SRAM banks, and parallel tag/data access. The shared L2 is distributed across tiles, with each L2 slice having its own directory entries. Coherence traffic traverses a 2D mesh NoC in which each tile embeds three routers: request, response, and directory. The default NoC data-path width is 64 bits, but it is parametrically configurable up to 704 bits for wider streaming channels.

The access-time model is summarized in the REPTILES paper as follows:

• L1 hit latency: $\mathrm{IPC} \approx 0.9$7 cycle
• L1 miss penalty to L1.5: $\mathrm{IPC} \approx 0.9$8 cycles
• L1.5 miss penalty to L2: $\mathrm{IPC} \approx 0.9$9 cycles plus NoC traversal
• L2 miss penalty to HBM: $$\mathrm{IPC} = \frac{\mathrm{instructions\_retired}}{\mathrm{cycles\_elapsed}},$$0–150 cycles

Overall access time is expressed as

$$\mathrm{IPC} = \frac{\mathrm{instructions\_retired}}{\mathrm{cycles\_elapsed}},$$1

where $$\mathrm{IPC} = \frac{\mathrm{instructions\_retired}}{\mathrm{cycles\_elapsed}},$$2 is the local cache-level hit rate. The textual schematic in the paper further indicates that each mesh node combines the Sargantana CPU, the L1 I-cache and HPDcache, and the L1.5 cache with the NoC routers. A plausible implication is that Sargantana’s role in REPTILES is defined as much by its memory-system attachment and coherence participation as by its scalar or vector execution pipeline.

5. Scalability and measured performance

The REPTILES evaluation uses an FPGA prototype on a Xilinx Alveo U55C with 4 $$\mathrm{IPC} = \frac{\mathrm{instructions\_retired}}{\mathrm{cycles\_elapsed}},$$3 Sargantana cores running at approximately 300 MHz, a frequency limited by the FPGA. The reported cache hierarchy is 16 KB L1I, 16 KB HPDcache, 32 KB L1.5, and 64 KB L2, with 64 B cache lines and 64 MSHRs; the platform also includes 16 GB HBM main memory, Ethernet, and an SDV filesystem for live demos (Oliete-Escuín et al., 6 May 2026).

Scalability is evaluated with NAS Parallel Benchmarks under Linux using OpenMP. The paper defines speedup and efficiency as

$$\mathrm{IPC} = \frac{\mathrm{instructions\_retired}}{\mathrm{cycles\_elapsed}},$$4

The listed benchmark set includes CG, EP, MG, FT, SP, LU, and BT. The reported average speedups are approximately $$\mathrm{IPC} = \frac{\mathrm{instructions\_retired}}{\mathrm{cycles\_elapsed}},$$5, $$\mathrm{IPC} = \frac{\mathrm{instructions\_retired}}{\mathrm{cycles\_elapsed}},$$6, and $$\mathrm{IPC} = \frac{\mathrm{instructions\_retired}}{\mathrm{cycles\_elapsed}},$$7, with CG and EP reaching $$\mathrm{IPC} = \frac{\mathrm{instructions\_retired}}{\mathrm{cycles\_elapsed}},$$8 at 4 threads.

For single-core vector evaluation, the paper reports an 8-bit integer vector-addition microbenchmark with $$\mathrm{IPC} = \frac{\mathrm{instructions\_retired}}{\mathrm{cycles\_elapsed}},$$9 elements. The scalar version takes $\mathrm{CPI} = \frac{1}{\mathrm{IPC}}.$0 and the RVV version takes $\mathrm{CPI} = \frac{1}{\mathrm{IPC}}.$1, yielding

$\mathrm{CPI} = \frac{1}{\mathrm{IPC}}.$2

The paper also reports thread spawn/join overhead of approximately 2 ms per OpenMP parallel region and pipeline-stall overhead for non-vectorized loops of approximately 0.1 cycle per instruction.

These measurements matter because they separate two effects often conflated in multicore discussions. One effect is thread-level scaling across multiple Sargantana tiles under OpenMP; the other is data-level acceleration within a single core through RVV execution. The published results show both, with the former summarized by the NAS speedups and the latter by the vector-addition microbenchmark.

6. Comparative position, trade-offs, and recurring misunderstandings

The REPTILES paper compares Sargantana-based REPTILES against baseline OpenPiton and against other open-source RISC-V cores. Relative to baseline OpenPiton, REPTILES adds RVV v1.0, HPDcache, and a wider NoC path up to 704 bits. For HPC workloads, the paper reports that 4-core NAS speedup improves from approximately $\mathrm{CPI} = \frac{1}{\mathrm{IPC}}.$3 in baseline OpenPiton to $\mathrm{CPI} = \frac{1}{\mathrm{IPC}}.$4 in REPTILES. Relative to Rocket, which is described as in-order and without vector support, the paper states that Rocket’s 5-stage pipeline achieves $\mathrm{CPI} = \frac{1}{\mathrm{IPC}}.$5 on similar workloads, whereas Sargantana sustains $\mathrm{CPI} = \frac{1}{\mathrm{IPC}}.$6 and adds RVV. Relative to BOOM, which is out-of-order, the paper states that BOOM can reach $\mathrm{CPI} = \frac{1}{\mathrm{IPC}}.$7 but at the cost of approximately $\mathrm{CPI} = \frac{1}{\mathrm{IPC}}.$8 area and approximately 50% more power (Oliete-Escuín et al., 6 May 2026).

The same source gives area, power, and frequency figures for Sargantana on 22 nm: 1.26 GHz nominal, approximately 1.5 mm² per core, and approximately 200 mW at full rate. The FPGA prototype runs at approximately 300 MHz and is limited by BRAM and routing. OpenPiton plus the REPTILES NoC and caches add approximately 20% area overhead over baseline OpenPiton.

Several recurrent misunderstandings are addressed directly by the published descriptions. First, Sargantana should not be categorized as an out-of-order superscalar core: both papers identify it as in-order, even though one variant includes register renaming and out-of-order write-back (Bandera et al., 2024). Second, the REPTILES version should not be read as implementing full RVV floating-point functionality, because scalar vector FP is explicitly stated as not yet implemented (Oliete-Escuín et al., 6 May 2026). Third, the HUB-adder integration should not be read as full IEEE-754 compatibility, because the paper explicitly excludes subnormals, alternative rounding modes, tie-to-even enforcement, and full exception/status handling (Bandera et al., 2024).

Taken together, the two papers position Sargantana as an open-source, resource-conscious RISC-V design whose distinguishing features are not extreme speculative execution but rather a combination of Linux capability, vector support, custom arithmetic extensibility, and systematic integration into a tiled coherent memory hierarchy.