Floating Point HUB Adder for RISC-V Sargantana Processor

Published 8 Jan 2024 in cs.AR | (2401.09464v1)

Abstract: HUB format is an emerging technique to improve the hardware and time requirement when round to nearest is needed. On the other hand, RISC-V is an open-source ISA that many companies currently use in their designs. This paper presents a tailored floating point HUB adder implemented in the Sargantana RISC-V processor.

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