REPTILES: Repeated Tiles of Sargantana, a RISC-V multicore based on OpenPiton

Abstract: Chip industry continues advancing and expanding modern computing systems, resulting in more complex multi-core processors. Conversely, academic projects face scalability challenges due to limited resources, highlighting the need for open-source frameworks that enable innovation and knowledge sharing. Recently, several open-source proposals have emerged, offering flexible and scalable designs, but fail to meet the performance demands of modern High-Performance Computing (HPC) applications. In this project, we present REPTILES, an open-source RISC-V multicore framework based on OpenPiton\thanks. REPTILES interconnects multiple Sargantana cores with the memory hierarchy of OpenPiton. Moreover, we present the new features incorporated in Sargantana and OpenPiton designs to improve the performance of HPC applications. We demonstrate that REPTILES presents suitable scalability, achieving a speedup of 3.1x on average with 4 cores. Additionally, we show that Sargantana's new features increase the performance of vector addition benchmark in a 9.3x.

• The paper demonstrates that integrating Sargantana RISC-V cores with a configurable cache hierarchy and parametric NoC achieves notable HPC speedups (up to 3.6x).
• It validates the architecture on FPGA prototyping (Xilinx Alveo u55), proving its scalability and robustness for academic HPC workloads.
• The upgrade from RVV 0.7 to RVV 1.0 with enhanced vector operations and debugging features paves the way for future open-source multicore research.

Overview of REPTILES: An Open-Source RISC-V Multicore for High-Performance Computing

Context and Motivation

The advancement of heterogeneous and multicore processors in the semiconductor industry has amplified the complexity and performance requirements of modern computing systems, particularly in HPC domains. Nevertheless, resource constraints in academia have impeded comparable progress, thereby reinforcing the necessity for highly customizable, scalable open-source frameworks that can meet contemporary HPC demands. While noteworthy open-source multicore frameworks—such as OpenPiton—have been developed, they often exhibit performance bottlenecks that inhibit broader applicability to compute-intensive workloads.

Architectural Contributions

REPTILES (REPeated TILEs of Sargantana) is introduced as an open-source multicore design that leverages and extends OpenPiton’s infrastructure, interfacing it with Sargantana RISC-V cores. The architecture is characterized by the following key design elements:

• Sargantana Tiles: Each REPTILES tile incorporates a Sargantana 64-bit in-order RISC-V processor (RV64G), now featuring significant advances, especially in vector processing.
• Memory Hierarchy: The system integrates a hierarchical cache design—private L1 instruction and HPD data caches, an L1.5 cache, and a shared distributed L2 cache—supported by directory-based MESI protocol coherence and parametric configurability for cache size, associativity, MSHRs, and parallel SRAM access.
• Network-on-Chip: A parametric NoC design with scalable width (64 to 704 bits) ensures efficient interconnect bandwidth, critical for multicore scalability and memory subsystem throughput in HPC workloads.
• FPGA Prototyping: REPTILES is prototyped on Xilinx Alveo u55 FPGA, supporting up to 4 Sargantana tiles with 16 GB HBM and Ethernet connectivity, forming a robust SDV environment for research and benchmarking.

Key Architectural Enhancements

Significant new open-sourced features in both OpenPiton and Sargantana are highlighted:

• OpenPiton Enhancements: Parametric NoC width, configurable cache block sizes (64, 32, 16 bytes), and substantial improvements in cache configuration further increase suitability for HPC.
• Sargantana Improvements: The most substantial architectural improvement is the full upgrade from RVV 0.7 to RVV 1.0, encompassing broader vector instruction support (except LMUL > 1 and vector FP), with the addition of register renaming for vector configuration instructions. Debugging (Sdext) and precise performance monitoring through Sscofpmf are also introduced, as well as checkpointing for the Verilator-based simulation environment.

Quantitative Evaluation

The performance of REPTILES is empirically evaluated using the NAS Parallel Benchmarks under Linux via OpenMP, with strong scalability demonstrated:

• Multicore Scalability: With 4 Sargantana cores, REPTILES achieves a mean speedup of 3.1x relative to single-threaded execution; CG and EP benchmarks exhibit speedups up to 3.6x.
• Vector Performance: The RVV-enhanced Sargantana core exhibits a 9.3x speedup relative to the scalar processing core on an 8-bit vector addition benchmark.

These results substantiate the claim that REPTILES, through a modular yet performant tile-based multicore approach, is well-suited for academic HPC workloads and surpasses many prior open-source proposals in both accessibility and throughput.

Theoretical and Practical Implications

REPTILES represents a substantial advance in academic hardware research infrastructure. The ability to experiment with vector-processing optimizations and full system-on-chip (SoC) prototyping addresses a persistent capability gap for performance-oriented HPC hardware research. The newly open-sourced enhancements—especially the broader RVV support, NoC tailoring, and cache subsystem configurability—offer an extensible baseline for both software-hardware co-design and architecture-level exploration at scale.

From a practical perspective, the open availability of both hardware and simulation enhancements in REPTILES will expedite both architectural research and systems software development for new RISC-V based HPC deployments. The detailed Verilator checkpointing can accelerate large-scale design-space explorations, fostering rapid prototyping and reducing simulation overhead for extended workloads.

Outlook and Future Directions

REPTILES’s architecture and open-source licensing invite widespread adoption and further extensions from the academic community. Forthcoming research may channel development into broader core counts, improved support for SIMD and floating-point vector instructions, and deeper exploration of memory system optimizations, including emerging non-volatile or disaggregated memory models. The demonstrated speedups suggest that further investment in architectural tuning and core microarchitecture features could deliver even greater gains, particularly as the RISC-V community standardizes and proliferates new ISA extensions and accelerator interfaces.

In addition, the integration with high-bandwidth memory (HBM) and the comprehensive support for software development environments ensure that REPTILES can serve as an effective experimental platform for software-hardware co-design at the microarchitectural, system, and application layers.

Conclusion

REPTILES demonstrates that open-source multicore frameworks based on RISC-V and modular tile-based architectures can achieve robust scalability and performance for HPC workloads, previously largely unattainable in academic settings. The architecture's configurability, extensive vector processing support, and detailed open evaluation position it as a relevant platform for ongoing collaborative research and rapid prototyping across the hardware-software stack. The project fundamentally lowers the barrier for academic exploration in the design and study of modern high-performance computing systems.