MCv3: RISC-V HPC Testbed

• Monte Cimone v3 (MCv3) is a RISC-V HPC cluster featuring 64 cores at 2.6 GHz with full RVV 1.0 vector support, enhanced memory channels, and a re-partitioned L2 cache for improved throughput.
• Benchmark evaluations using HPL and STREAM Triad reveal over 2× single-core performance gains and sustainable memory bandwidth of 150–165 GB/s under topology-aware configurations.
• Architectural enhancements such as a 32-channel LPDDR5X subsystem and rigorous power measurement yield an energy efficiency of 3.08 GFLOPs/W, positioning MCv3 competitively with modern x86-64 and Arm servers.

Monte Cimone v3 (MCv3) is the third iteration of the Monte Cimone RISC-V high-performance computing testbed, presented as a RISC-V HPC cluster based on the SOPHGO Sophon SG2044 processor, an evolution of the SG2042 used in MCv2. The platform is characterized with HPL and STREAM benchmarks coupled with power measurements and is compared against two reference platforms, the Intel Xeon Platinum 8480+ (Sapphire Rapids) and the NVIDIA Grace CPU Superchip. In the reported evaluation, the SG2044 more than doubles single-core performance relative to SG2042, improves scalability, and enables MCv3 to reach an energy efficiency of 3.08 GFLOPs/W, a $10\times$ improvement with respect to MCv1 and a value described as being in the range of contemporary x86-64 and Arm servers (Venieri et al., 22 Apr 2026).

1. Position within the Monte Cimone lineage

MCv3 is explicitly situated as the successor to two earlier Monte Cimone systems. MCv1 is described as using a proprietary R-class RISC-V SoC with approximately 32 cores, no vector extension, and single-digit GB/s memory bandwidth. MCv2 is based on the SG2042, with 64 cores, an early RVV draft with 64-bit vector length, 8 LPDDR5X channels, and modest scaling. MCv3 retains the 64-core count but moves to full RVV 1.0 with 128-bit vectors, $4\times$ more memory channels, and an improved L2 hierarchy (Venieri et al., 22 Apr 2026).

This progression is central to the paper’s framing of where RISC-V stands in HPC. The comparison across MCv1, MCv2, and MCv3 is not only generational but architectural: vector support, memory-system width, and cache organization all change in ways that are intended to make the platform more relevant to throughput-oriented scientific workloads. A plausible implication is that the Monte Cimone series is used less as a production cluster than as a controlled longitudinal testbed for tracking how successive RISC-V server-class designs close specific gaps relative to established HPC CPUs.

2. Node architecture and software environment

MCv3 comprises two compute nodes in the SLURM “Peak” partition, with each node housing a SOPHGO Sophon SG2044 SoC. Each SG2044 integrates 64 RISC-V cores at 2.6 GHz and provides full RVV 1.0 vector support. The processor is described as implementing an 8-stage in-order pipeline with high-throughput FMA units, a 128-bit maximum vector length, and support for $2 \times 64$-bit doubles per vector. On chip, each core has private L1 instruction and data caches, while each 16-core cluster shares a 1 MiB L2. Off chip, each node exposes 128 GiB of memory via 32 LPDDR5X channels. Both nodes attach to the existing InfiniBand/Ethernet cluster interconnect and are managed under SLURM, sharing NFS-exported home directories and a Spack-based software stack (Venieri et al., 22 Apr 2026).

These details matter because MCv3’s reported behavior is tied closely to the SoC’s memory topology and vector ISA realization. Relative to SG2042, the SG2044’s transition from an early RVV draft to full RVV 1.0 and from 8 to 32 LPDDR5X channels is presented as an architectural rather than merely incremental revision. The paper also attributes part of the improvement to L2-cluster re-partitioning, which is reported to improve data locality under OpenMP. In this sense, MCv3 is a system-level embodiment of several concurrent RISC-V maturation steps: a standards-based vector implementation, a wider memory subsystem, and a cache hierarchy organized around 16-core clusters.

3. Benchmarking and measurement protocol

The evaluation uses HPL (High-Performance LINPACK) for floating-point performance and STREAM Triad for sustainable memory bandwidth. The software stack is reported as GCC 14.2 with -O3 and architecture-specific flags, together with OpenBLAS 0.3.29 on all platforms; the paper explicitly notes that there is no vendor-tuned BLAS for SG2044. For STREAM, the array size is scaled to exceed last-level cache, and OpenMP thread counts are swept from 1 to 64 under both naïve and L2-aware thread pinning. For HPL, the problem size is chosen to fill at least 90% of node memory, block size is tuned per architecture, and runs are MPI-only with one process per core and a sweep from 1 to 64 ranks. Power on MCv3, Intel Sapphire Rapids, and NVIDIA Grace is measured at platform level via IPMI sampled at 1 Hz, with steady-state averages taken over the main kernel phase; MCv1 instead uses board-level shunt-based instrumentation. All reported efficiencies include only compute-node power and exclude facility overheads (Venieri et al., 22 Apr 2026).

The methodological choices constrain how the results should be interpreted. The use of a common compiler and a common OpenBLAS release emphasizes cross-platform comparability, while the absence of a vendor-tuned BLAS for SG2044 limits the extent to which MCv3 can be seen as fully software-optimized. Similarly, the paper’s explicit attention to thread pinning in STREAM indicates that cache-cluster placement is not incidental but part of the effective programming model. This suggests that topology-aware runtime configuration is already significant for extracting performance from current RISC-V server-class parts.

4. Floating-point and memory performance

The single-node HPL results place MCv3 substantially ahead of earlier Monte Cimone systems, while still below the absolute throughput of the Intel and NVIDIA reference platforms.

Platform	HPL [GFLOPs]	Achieved / Peak
MCv1	1.86	14.5%
MCv2 (SG2042)	121	72.7%
MCv3 (SG2044)	258.0	77.5%
Intel SR	4 928	42.9%
NVIDIA GS	3 769	50.3%

The paper reports that MCv3 exhibits near-linear HPL scaling up to 16 cores, followed by mild sub-linear behavior beyond that point as inter-core memory contention rises. It also reports that MCv3 delivers more than $2\times$ single-core performance relative to MCv2 and a $139\times$ improvement over MCv1 (Venieri et al., 22 Apr 2026).

The STREAM Triad measurements show a similarly strong generational change in sustainable bandwidth. At 16 threads, MCv3 reaches 150 GB/s, compared with 50 GB/s for MCv2 and 0.5 GB/s for MCv1; at 64 threads, MCv3 reaches 165 GB/s, compared with 60 GB/s for MCv2 and 1 GB/s for MCv1. For reference, Intel Sapphire Rapids is reported at 275 GB/s and 470 GB/s at 16 and 64 threads respectively, while NVIDIA Grace reaches 545 GB/s and 1 030 GB/s. MCv3 is reported to saturate STREAM bandwidth already at 16 threads under L2-aware pinning, with absolute bandwidth $2.6\times$ that of MCv2 and $100\times$ that of MCv1 (Venieri et al., 22 Apr 2026).

Taken together, these results establish a distinctive performance profile. MCv3’s absolute HPL throughput remains far below that of the Intel and NVIDIA server CPUs, but its achieved/peak fraction is higher than on those reference platforms. This suggests that comparisons based only on raw GFLOPs can miss how efficiently the available compute and memory resources are being used on a narrower-vector RISC-V design.

5. Energy efficiency and vector-length-normalized comparison

Energy efficiency is defined as HPL performance in GFLOPs divided by power in watts, yielding GFLOPs/W. Under this definition, the reported single-node results are as follows.

Platform	Avg Power [W]	$\eta$ [GFLOPs/W]
MCv1	5.9	0.31
MCv3	83.9	3.08
NVIDIA GS	828	4.55
Intel SR	1 276	3.86

MCv3’s 3.08 GFLOPs/W corresponds to a $10\times$ gain over MCv1. The paper states that this places MCv3 in the range of modern x86-64 and Arm servers, specifically between Intel Sapphire Rapids at 3.86 GFLOPs/W and NVIDIA Grace at 4.55 GFLOPs/W (Venieri et al., 22 Apr 2026).

The paper also introduces a normalization of performance by SIMD/vector length, where $L$ denotes vector length in bits. At the 16-core “sweet spot,” described as MCv3’s peak efficiency point, the normalized result reaches 46% of Intel Sapphire Rapids and 91% of the NVIDIA Grace CPU Superchip. The references are AVX-512 with $4\times$0-bit vectors for Intel and SVE2 with $4\times$1-bit vectors for Grace. This normalization is important because it reframes the comparison from absolute socket-level throughput to the efficiency with which different vector-width regimes are converted into application-level performance. A plausible implication is that MCv3 compares more favorably when the analysis controls for ISA-level vector width rather than treating wider-SIMD designs as directly commensurate.

6. Architectural interpretation, bottlenecks, and projected evolution

The paper attributes MCv3’s improvement to three principal architectural drivers: RVV 1.0 vectors and 128-bit lanes, which double floating-point throughput relative to SG2042’s 64-bit vectors; a 32-channel LPDDR5X memory subsystem, which increases aggregate bandwidth and reduces per-core pressure; and L2-cluster re-partitioning, which improves data locality under OpenMP. These factors align with the reported HPL and STREAM results, particularly the strong increase in single-core performance and the early saturation of memory bandwidth under topology-aware thread placement (Venieri et al., 22 Apr 2026).

At the same time, several bottlenecks are identified. Memory-bandwidth contention beyond 16 cores limits strong scaling. The lack of a shared L3 or on-chip mesh is reported to exacerbate inter-cluster communication. In addition, the network topology—a 2-node partition—hides interconnect latency effects, so the study does not expose the full behavior of the platform under more demanding multi-node HPC communication patterns. These constraints delimit the extent to which MCv3 can be generalized from node-level kernels to broader distributed-memory workloads.

The future directions named for “MCv4+” are wider vector units, such as 256-bit vectors or SVE-style scalable vectors; on-chip mesh or NUMA domains to improve high-core-count scaling; and hardware-accelerated collective communications for multi-node HPC runs. These directions are consistent with the bottlenecks observed in MCv3. They also indicate that, within the paper’s perspective, the remaining gap is not attributed to a single issue but to the combined interaction of vector width, memory scaling, and inter-core or inter-node communication. In that sense, MCv3 is presented less as an endpoint than as evidence that a commodity RISC-V processor can now deliver multi-hundred-GFLOP HPL runs with energy efficiency competitive with Intel and NVIDIA platforms, while still exposing the system-level challenges that must be resolved for broader HPC adoption.