EPAC: Multidisciplinary Applications Overview

• EPAC is an acronym with varied definitions across domains, including accelerator physics, software-process engineering, VSG control, and RISC-V chip design.
• Each EPAC usage employs specialized methods—from magnetic beam transport modeling and process tailoring via process lines to transient stability analysis and simulation via QEMU+RAVE.
• Practical implications span improved energy confinement, efficient software customization, robust inverter stability, and advanced high-performance processor validation.

Searching arXiv for the relevant EPAC usages and papers to ground the article. EPAC is an acronym used in the cited literature for several technically distinct constructs rather than for a single unified framework. In accelerator physics, it appears as the conference context for work on beam transport in a toroidal magnetic field (Joshi et al., 2016). In software-process engineering, EPAc denotes the Emergent Process Acquisition method for project-specific process tailoring (Jaufman et al., 2014). In power-electronics control, EPAC denotes the Equal Proportional Area Criterion for analyzing the transient stability impact of current-limiting strategies in virtual synchronous generators (Zhao et al., 2024). In high-performance processor design, EPAC denotes the European Processor Accelerator project and, more specifically, a silicon-proven RISC-V-based accelerator chip developed within the European Processor Initiative (Vizcaino et al., 2024, Mantovani et al., 14 Apr 2026).

1. Scope and disambiguation

In the available research record, the acronym is overloaded across multiple domains. The principal usages documented in the cited sources are summarized below.

Usage	Domain	Source
EPAC conference context for toroidal-field beam transport	Accelerator physics	(Joshi et al., 2016)
Emergent Process Acquisition method (EPAc)	Software-process engineering	(Jaufman et al., 2014)
Equal Proportional Area Criterion (EPAC)	VSG transient-stability analysis	(Zhao et al., 2024)
European Processor Accelerator (EPAC) project and chip	RISC-V HPC accelerators	(Vizcaino et al., 2024, Mantovani et al., 14 Apr 2026)

A common misconception is to treat EPAC as a single technology family. The cited papers instead show that the acronym spans at least four unrelated research settings: conference proceedings in accelerator physics, a method for software-process tailoring, a stability criterion for inverter control, and a European RISC-V accelerator effort. Technical interpretation therefore depends entirely on disciplinary context.

2. Accelerator-physics usage: toroidal magnetic-field beam transport

In the accelerator-physics paper, EPAC appears as the conference context in which the storage-ring concept had previously been presented. The reported system is a novel ion-storage ring based on a figure-8 stellarator-type configuration in which a toroidal magnetic field confines intense ion beams from 100 keV to a few MeV. The fully three-dimensional geometry closes magnetic surfaces, compensates the transverse $R \times B$ drift, and in principle allows multi-turn accumulation up to Brillouin-limit currents,

$n_B = \epsilon_0 B^2 /(2 m).$

For $B=5\ \mathrm{T}$ and $150\ \mathrm{keV}$ energy, this corresponds to $J \approx 5.6\ \mathrm{A/cm^2}$ (Joshi et al., 2016).

The technical summary identifies the principal challenges as curvature-induced $R \times B$ drift, field-line torsion, multi-pulse injection into an already circulating beam, fringing fields of unshielded toroidal segments, and the 0.6 T field ceiling of the present test segments, which limits the acceptable ion-energy range to approximately 4–20 keV for proton transport experiments. Two identical iron-core magnets, each subtending $30^\circ$ of a 1.3 m major-radius ring, were built. Their key parameters are $R_0 = 1\,300\ \mathrm{mm}$, minor radius $a = 100\ \mathrm{mm}$, central arc length $\simeq 680\ \mathrm{mm}$, and on-axis field $n_B = \epsilon_0 B^2 /(2 m).$0 at $n_B = \epsilon_0 B^2 /(2 m).$1. Neglecting end effects, the bore field is idealized as

$n_B = \epsilon_0 B^2 /(2 m).$2

Fringing regions extend about 100 mm beyond each coil end and were included in both 3D magnetic mapping and PIC simulations.

The injection region combines a transverse injection coil system $n_B = \epsilon_0 B^2 /(2 m).$3, aperture 300 mm, with an electric kicker of plate length $n_B = \epsilon_0 B^2 /(2 m).$4 up to 20 cm. The multi-turn injection principle uses the coils to superpose an auxiliary transverse magnetic field $n_B = \epsilon_0 B^2 /(2 m).$5 that opens a window in the main toroidal flux surface, while an electric kicker supplies an $n_B = \epsilon_0 B^2 /(2 m).$6 drift to shift particles back toward the stored-beam flux tube. The drift velocity is

$n_B = \epsilon_0 B^2 /(2 m).$7

and the vertical drift over the plate length is

$n_B = \epsilon_0 B^2 /(2 m).$8

At $n_B = \epsilon_0 B^2 /(2 m).$9, empirical optimization yielded $B=5\ \mathrm{T}$0.

Transport quality was characterized by a “good-beam” condition defined through the velocity ratio

$B=5\ \mathrm{T}$1

Particles satisfying this condition remain magnetically confined, while those with larger transverse velocities are lost as “trapped.” Experimentally, a volume-type ion source extracted up to 3.08 mA of protons at 10 keV, and the measured emittance matched PIC simulations through the 0.72 T matching solenoid. At 12 keV, the beam species composition was approximately $B=5\ \mathrm{T}$2, $B=5\ \mathrm{T}$3, and $B=5\ \mathrm{T}$4. For $B=5\ \mathrm{T}$5 and $B=5\ \mathrm{T}$6–$B=5\ \mathrm{T}$7, a good-beam signal was recorded. Output beam radii were reported as $B=5\ \mathrm{T}$8 and $B=5\ \mathrm{T}$9, and angular divergence and phase-space ellipses agreed to within $150\ \mathrm{keV}$0 between measurement and simulation under the good-beam criterion. For injection into the second segment, a 10 mm diameter, 2 mA, 10 keV proton beam with $150\ \mathrm{keV}$1 could be injected through $150\ \mathrm{keV}$2 into segment 2 with greater than 90% capture probability in simulation.

3. EPAc as Emergent Process Acquisition in software-process engineering

In software-process engineering, EPAc is the Emergent Process Acquisition method, proposed in response to the observation that generic, monolithic development processes were often considered too generic for operational use and could not be tailored quickly enough to changing project contexts. The method combines a disciplined top-down tailoring of a domain-specific process line with a bottom-up refinement driven by the team’s actual performance data. The work described was conducted in the automotive domain, and the expected advantages were tailoring efficiency gained by usage of a process line and higher process adherence gained by bottom-up adaptation of the process (Jaufman et al., 2014).

The top-down phase is organized around a process line

$150\ \mathrm{keV}$3

where $150\ \mathrm{keV}$4 is the common core of activities and milestones, $150\ \mathrm{keV}$5 is a set of process variants, and $150\ \mathrm{keV}$6 is a set of variability relations and constraints. A single variant is modeled as

$150\ \mathrm{keV}$7

where $150\ \mathrm{keV}$8 is the set of additions, removals, or replacements from the core. Constraints have the form

$150\ \mathrm{keV}$9

and the tailoring function is expressed as

$J \approx 5.6\ \mathrm{A/cm^2}$0

with $J \approx 5.6\ \mathrm{A/cm^2}$1 denoting a vector of project drivers such as team experience, criticality, tool-chain, and schedule pressure. Tool-supported tailoring proceeds through three sub-steps: selecting alternatives and building the process line, finding the needed abstraction level through an abstraction index $J \approx 5.6\ \mathrm{A/cm^2}$2, and interactively selecting deviations to yield the initial prescriptive skeleton $J \approx 5.6\ \mathrm{A/cm^2}$3.

The bottom-up phase logs actual activity completion and timestamps through the coordination tool InStep. EPAc converts textual logs into a well-formed XML event log $J \approx 5.6\ \mathrm{A/cm^2}$4, applies process mining with ProM to induce the executed model $J \approx 5.6\ \mathrm{A/cm^2}$5, and computes

$J \approx 5.6\ \mathrm{A/cm^2}$6

A simple adherence metric is

$J \approx 5.6\ \mathrm{A/cm^2}$7

with values near 1 indicating high conformance. The method also distinguishes minimal-requirement elements $J \approx 5.6\ \mathrm{A/cm^2}$8 from optional ones $J \approx 5.6\ \mathrm{A/cm^2}$9; when $R \times B$0, the tool forces a justification from the project manager before deleting or deferring those elements. The overall EPAc workflow has five steps: process selection and line construction, abstraction-level cut, interactive variant selection, first-iteration execution and logging, and reflection and refinement to produce a refined process $R \times B$1.

The initial validation used 28 advanced students building a bus-door-and-lighting control system over three 4-week iterations. Two emergent groups used EPAc, and one group used a conventionally tailored V-Model process. Metrics were defined via GQM: productivity as total person-minutes per activity type, product quality as incorrectly implemented critical and non-critical features plus design-clarity scores, and team satisfaction as a 5-point survey aggregated per group. The reported results were that the V-Model group’s total effort was 20–30% higher each week than the Emergent groups, V-Model prototypes missed 2–3 more critical features per iteration on average, and Emergent teams reported higher overall satisfaction, with mean approximately 1.8/2 versus approximately 1.1/2. In the bus-control mini-case, cutting to $R \times B$2 left about 28 possible tasks; after removing optional reviews and adding one new emergency-stop validation task, $R \times B$3 became a 6-milestone, 18-task prescriptive plan. During execution, the conformance check found $R \times B$4 and $R \times B$5, yielding

$R \times B$6

4. EPAC as Equal Proportional Area Criterion in VSG control

In the VSG-control paper, EPAC denotes the Equal Proportional Area Criterion, used to explain how different current-limiting strategies affect transient stability and to design a new effective current-limiting strategy. The underlying VSG dynamics are given by the swing equation

$R \times B$7

where $R \times B$8 is the mechanical power reference input, $R \times B$9 is the electrical output power as a function of power angle $30^\circ$0, $30^\circ$1 is the virtual inertia, $30^\circ$2 is the damping coefficient, $30^\circ$3 is the instantaneous virtual rotor speed, $30^\circ$4 is the nominal grid frequency, and $30^\circ$5. Neglecting damping for an intuitive first pass gives

$30^\circ$6

The accelerating and decelerating areas are then defined as

$30^\circ$7

and

$30^\circ$8

The system is marginally stable if and only if $30^\circ$9; if $R_0 = 1\,300\ \mathrm{mm}$0, it returns to synchronism, otherwise it loses synchronism (Zhao et al., 2024).

Under normal conditions, the VSG–inverter output power is

$R_0 = 1\,300\ \mathrm{mm}$1

When the inverter current reference would exceed $R_0 = 1\,300\ \mathrm{mm}$2, the current limiter clips the power-angle curve. Three legacy current-limiting schemes are analyzed. Angle-priority CL holds the current-phasor angle constant and reduces the magnitude to $R_0 = 1\,300\ \mathrm{mm}$3, yielding the piecewise form

$R_0 = 1\,300\ \mathrm{mm}$4

Graphically, the clipped portion truncates the sine curve symmetrically about $R_0 = 1\,300\ \mathrm{mm}$5, reducing $R_0 = 1\,300\ \mathrm{mm}$6 and increasing $R_0 = 1\,300\ \mathrm{mm}$7. d-axis-priority CL attempts to keep $R_0 = 1\,300\ \mathrm{mm}$8 unchanged while reducing $R_0 = 1\,300\ \mathrm{mm}$9, again enlarging the accelerating area relative to the decelerating area. q-axis-priority CL keeps $a = 100\ \mathrm{mm}$0 unchanged and reduces $a = 100\ \mathrm{mm}$1, yielding the smallest reduction of $a = 100\ \mathrm{mm}$2 in the accelerating region and therefore the smallest $a = 100\ \mathrm{mm}$3 among the three. The stability margin is quoted as

$a = 100\ \mathrm{mm}$4

The proposed adaptive current-limiting strategy sets the post-limit current-phasor angle to

$a = 100\ \mathrm{mm}$5

so that the limited current references become

$a = 100\ \mathrm{mm}$6

This forces the clipped power curve to

$a = 100\ \mathrm{mm}$7

that is, a constant-power limit at $a = 100\ \mathrm{mm}$8. The stated rationale is that the accelerating area is minimized while, after fault clearance, the limiter is immediately released and the decelerating area remains unchanged. MATLAB/Simulink validation used $a = 100\ \mathrm{mm}$9, $\simeq 680\ \mathrm{mm}$0, $\simeq 680\ \mathrm{mm}$1, $\simeq 680\ \mathrm{mm}$2, and $\simeq 680\ \mathrm{mm}$3, with a three-phase fault applied at 0.50 s and cleared at 0.80 s. The numerical areas were reported as

$\simeq 680\ \mathrm{mm}$4

for q-axis CL and

$\simeq 680\ \mathrm{mm}$5

for the adaptive CL, with the former unstable and the latter stable.

5. EPAC as the European Processor Accelerator project: simulation and vector-execution analysis

Within the European Processor Initiative, EPAC also denotes the European Processor Accelerator project. One of the project’s toolchain contributions is RAVE, the RISC-V Analyzer of Vector Executions, implemented as a QEMU tracing plugin to address the project’s simulation needs. The paper identifies several limitations of the existing simulation solutions: Vehave only captures vector instructions when they fault on a scalar core, scalar counts must be inferred from noisy hardware counters, SIGILL-based execution incurs very high overhead in hot loops, and access to a real RISC-V board limits portability. FPGA RTL emulation provides cycle-accurate insight but is extremely slow and hard to integrate with trace tools. QEMU + RAVE is presented as providing full instruction-level transparency for both scalar and vector instructions without OS traps, single-step translation blocks with max_insns=1, portability to x86 or ARM hosts, and rich, self-contained vectorization traces in Paraver format together with end-of-run reports at a small overhead (Vizcaino et al., 2024).

The QEMU modifications are explicit: RV_VLEN_MAX is raised to 16 384 bits in target/riscv/cpu.h to match EPAC’s 16 kbit vectors, and translator_loop max_insns=1 is set in target/riscv/translate.c so each translation block contains exactly one instruction. The plugin disassembles the raw instruction, classifies it as scalar, vector, or tracing, builds an instr_data record for vector instructions, and attaches an execute-time callback that increments counters, appends a Paraver event record if tracing is enabled, and updates per-region summaries if execution is inside a user-defined region. The instr_data structure records PC, textual assembly, destination and source registers, a major vector type such as ARITH, MEMORY, or MASK, a minor type such as FP, INT, UNIT, STRIDE, or INDEX, and a Paraver event code.

RAVE maintains a qemu_counters structure with per-SEW counters for vector instructions, unit-strided memory operations, constant-stride operations, indexed operations, floating-point vector operations, integer vector operations, mask-only operations, and total vector elements operated, together with scalar and vsetvl counts. From these counters it computes

$\simeq 680\ \mathrm{mm}$6

the vector instruction mix

$\simeq 680\ \mathrm{mm}$7

the average vector length

$\simeq 680\ \mathrm{mm}$8

the vectorization factor

$\simeq 680\ \mathrm{mm}$9

and register utilization

$n_B = \epsilon_0 B^2 /(2 m).$00

The control API is encoded as writes to x0 with specific immediates, including qemu_start_trace(), qemu_stop_trace(), qemu_restart_trace(), event naming, and event/value pairs. At runtime, every traced instruction emits Paraver records, and the plugin writes both *.prv.def and *.prv files for timeline visualization and statistics.

The performance data separate synthetic and real-application behavior. In a synthetic benchmark of $n_B = \epsilon_0 B^2 /(2 m).$01 total instructions with varying vector-to-total ratio, QEMU+RAVE on AMD remained near 0.25–0.30 s while Vehave on HiFive rose from 0.15 s at zero vector instructions to 10.5 s at $n_B = \epsilon_0 B^2 /(2 m).$02 vector instructions per $n_B = \epsilon_0 B^2 /(2 m).$03 total instructions; the resulting speedup in the high-vector regime was approximately $n_B = \epsilon_0 B^2 /(2 m).$04. In real applications, graph kernels such as BFS, PR, CC, and SSSP showed QEMU+RAVE within 10–15% of Vehave, while vector-heavy kernels such as FFT and GEMM showed QEMU+RAVE at 0.6 s and 0.9 s versus Vehave at 0.8 s and 5.5 s, respectively. The overall speedup metric for GEMM was approximately $n_B = \epsilon_0 B^2 /(2 m).$05.

6. EPAC as a silicon-proven RISC-V accelerator chip

The 2026 EPAC chip paper presents EPAC as a RISC-V-based accelerator chip developed within the European Processor Initiative as part of a multi-year, multi-partner effort to build a European HPC processor ecosystem. The chip is implemented in GlobalFoundries 22FDX technology, covers an area of 27 sq mm with approximately 0.3 billion transistors, and integrates three distinct RISC-V compute tiles: VEC for double-precision HPC workloads, STX for stencil and machine-learning computations, and VRP for iterative numerical solvers requiring extended floating-point formats. All tiles are connected through a CHI-based network-on-chip with a distributed L2 cache system and communicate with external memory via a SerDes link. The chip was taped out in GF22FDX technology and successfully brought up, with all major IP blocks validated (Mantovani et al., 14 Apr 2026).

The VEC tile is built around an in-order RISC-V core, “Avispado,” with full Linux capability and an Open Vector Interface to a 0.7.1-compliant Vector Processing Unit. The VPU provides a 2048-byte maximum vector length, equivalent to 256 double-precision elements, eight parallel FAUST pipelined floating-point units processing eight DP elements per cycle, 40 physical vector registers, and full-width IEEE-754 DP support. The scalar core includes a 16 kB I-cache, 32 kB D-cache, and a Gazillion MSHR unit for at least 16 outstanding loads. Peak DP throughput per VEC tile is modeled as

$n_B = \epsilon_0 B^2 /(2 m).$06

which gives 8 GFLOPS at 1 GHz. The STX tile is a many-core accelerator with clusters of 4–16 RV32 Snitch cores, one DMA-capable Snitch, Stream Semantic Registers, local TCDM scratchpad of 64–256 kB per cluster, optional SPU co-processors tuned for static stencil patterns, and Floating-Point Repetition; an example configuration of 4 clusters by 8 Snitch cores at 1 GHz is reported as 64 GFLOPS DP per tile. The VRP tile is built from a CVA6 64-bit in-order core with Xvpfloat, a Variable-Precision FPU supporting up to 512-bit significand and 18-bit exponent, 64 physical to 32 logical P-registers with rename scoreboard, a chunked datapath, 16 kB I-cache, 32 kB HPDcache with programmable prefetcher and 128 outstanding misses, and runtime-configurable memory formats and internal precision.

The uncore deploys the AMBA 5 CHI protocol on a 2D mesh of programmable crosspoints. Each crosspoint has four mesh links and two device ports, dedicated request, response, data, and snoop channels, credit-based flow control, multicast support, and 512-bit data channels, yielding 64 B/cycle/port at 1 GHz. The distributed L2 hierarchy uses 256 kB slices, 8-way set associativity, write-back policy, 128 outstanding requests, pseudo-LRU, and a 512-bit data-array width so that one full 64 B cache line can be served per cycle. The L2-slice bandwidth is stated as

$n_B = \epsilon_0 B^2 /(2 m).$07

For off-chip memory, the chip uses a chip-to-chip SerDes link of 8 lanes at up to 25 Gb/s each, giving

$n_B = \epsilon_0 B^2 /(2 m).$08

or 50 GB/s bidirectional aggregate bandwidth.

Implementation and bring-up data are unusually explicit. The full chip is reported as 26.97 mm² active area plus 0.32 mm² scribe, with partition cell counts of 1.86 M for STX, 2.26 M for VEC, and 0.53 M for VRP, together with 991 SRAM macros from 16 kB to 256 kB. Timing corners are given as 768 MHz maximum at SS (0.72 V, 125 °C) and 1 234 MHz maximum at TT (0.80 V, 85 °C), with an operational target of 1 GHz at TT. Worst-case IR-drop is 47 mV, and DFT includes full scan, scan compression, and PMBIST via JTAG. The bring-up sequence covered JTAG/SPI register access and SRAM BIST, CHI/AXI inter-tile routing and coherence, VPU micro-benchmarks including DGEMM and STREAM, SerDes operation at a safe 20 GB/s aggregate to FPGA-attached DDR4/HBM, and OS boot of Ubuntu 22.04 with Linux 5.7(RISCV+V), including GUI, LINPACK, and scientific stacks. The paper closes with engineering lessons centered on interface discipline, tension between parameterized RTL and hierarchical place-and-route, the scheduling impact of DFT and test insertion, the value of hardware-software co-design in VRP, and the workload-dependent sweet-spots exposed by architectural diversity across VEC, STX, and VRP.