ASIC-Agent: Autonomous ASIC Design System

• ASIC-Agent is an autonomous multi-agent system that automates digital ASIC design workflows through specialized agents and LLM integration.
• It decomposes the design pipeline into focused modules for RTL generation, simulation, layout hardening, and SoC integration within a secure sandbox.
• ASIC-Agent-Bench offers a rigorous, checkpoint-based evaluation framework, benchmarking performance across diverse ASIC design tasks.

ASIC-Agent refers to an autonomous multi-agent system specifically developed for digital ASIC (Application-Specific Integrated Circuit) design workflows. The architecture leverages LLMs and a suite of specialized agents—responsible for RTL code generation, verification, hardening through OpenLane, and SoC integration—all operating in a controlled sandbox environment, with access to a vector database encompassing documentation, troubleshooting knowledge, and open silicon community insights. To facilitate systematic evaluation, the research introduces ASIC-Agent-Bench, a custom benchmark for assessing agentic systems on hardware design tasks across varying difficulty levels (Allam et al., 21 Aug 2025).

1. Multi-Agent System Architecture

ASIC-Agent decomposes the classical digital ASIC design pipeline into distinct sub-agents, each engineered to execute specialized functions within the workflow:

• Main Agent: Synthesizes RTL (Register Transfer Level) Verilog code from natural language specifications, ensuring correct module interfacing and signal logic. It also carries out linting and static analysis through integrated tools such as Verilator and iverilog to verify syntactic and design-rule compliance and orchestrates overall project state management.
• Verification Agent: Constructs functional simulation environments and test benches using Python-based cocotb and communicates with industry-standard simulators (Icarus Verilog, Verilator). It is responsible for executing simulations, identifying behavioral inconsistencies, analyzing root causes, and proposing corrections.
• Hardening Agent: Converts verified RTL into physical layouts, managing configuration files (config.json with variables such as CLOCK_PORT and CLOCK_PERIOD) and optimizing for PPA (Power, Performance, Area). The flow leverages OpenLane 2 and includes a log debugging sub-tool driven by a specialized LLM for parse-and-diagnose capability.
• Caravel Integration Agent: Integrates the finalized digital design with the Caravel SoC framework, generates wrapper modules, configures Wishbone memory-mapped registers, aligns pin and reset assignments to Caravel specifications, and ensures compliance with interface protocols.

System prompts and templates are assigned per agent to focus context and enhance task-specific reasoning. Central orchestration is achieved via an Agent-Computer Interface (ACI) enabling structured command execution for tasks such as simulation, synthesis, and documentation querying.

2. Sandbox Environment and Toolchain Integration

Deployment occurs within a secure Docker-based sandbox, preloaded with all required EDA (Electronic Design Automation) tools (Icarus Verilog, Verilator, Yosys, OpenLane). This closed environment supports:

• Direct interaction with toolchains for compilation, simulation, and layout hardening.
• Shell-level file and script manipulation (e.g., via run_test.sh).
• Dynamic iteration and modification of design artifacts under agent control.

The sandbox ensures reproducibility and isolates all workflow operations, emulating industrial ASIC design practice and facilitating detailed debugging and iterative design evolution.

3. Vector Database and Knowledge Augmentation

ASIC-Agent leverages a retrieval-augmented vector database to circumvent LLM limitations in context retention and domain specificity:

• Documentation Corpus: Semantic search over extensive hardware design tool documentation (including OpenLane, Caravel, cocotb).
• API and Error References: Rapid lookup of tool configuration, protocol interoperation details, and a curated error pattern database drawn from open-source silicon community reports.
• IP Block Insights: Instant retrieval of best practices and interface patterns for open-source IP block integration.

This combination of internal reasoning and external domain search equips agents with a highly informed, context-sensitive basis for decision making, enabling robust error handling and streamlined workflow progression.

4. Benchmark Methodology: ASIC-Agent-Bench

ASIC-Agent-Bench is introduced to rigorously evaluate agentic ASIC design workflows:

• Task Diversity: Includes both elementary design steps (counter generation, barrel shifters) and advanced processor-level design/integration tasks requiring full RTL to GDSII execution.
• Open-Ended Process: Emphasizes autonomy; agents structure their own workflows, including multi-file debugging, framework development, and dynamic tool invocation.
• Checkpoint-Based Grading: Partial credit is awarded upon achieving observable milestones (successful testbench execution, config.json generation, layout completion), with binary success metrics adjudicated by an LLM evaluator (gemini‑2.5‑pro).
• LLM-Powered Judgment: Narrative output and workflow traces are assessed contextually by an LLM, with task scores computed as weighted sums over milestones representing their real-world technical significance.

The benchmark is designed to expose both algorithmic strengths and limitations of agentic systems on practical digital ASIC design tasks.

5. Quantitative Evaluation Across LLM Backbones

Distinct base LLMs (Claude 4 Sonnet, GPT‑4.1, Gemini 2.5 Pro) were tested with ASIC-Agent on the ASIC-Agent-Bench:

LLM Variant	Avg. Score (%)	Steps Taken	Cost ($)
Claude 4 Sonnet	88	Moderate	Slightly High
GPT‑4.1	60.8	Fewer	Lower
Gemini 2.5 Pro	Middle Ground	Variable	Variable

Table entries correspond directly to reported data. High-complexity tasks yielded greater performance dispersion, with Claude 4 Sonnet maintaining high scores even on arduous multi-stage designs. Score computation reflects aggregate milestone achievement, not a single-point binary finish.

Performance analysis indicates that LLM selection impacts both the accuracy and efficiency of design flows under agentic control, with trade-offs between computational cost, speed, and solution quality.

6. Impact and Future Directions

ASIC-Agent demonstrates potential to substantially accelerate ASIC design workflows:

• Automates the entire RTL-to-physical integration pipeline, including functional verification, OpenLane layout hardening, and SoC packaging.
• Eliminates substantial manual intervention in debugging and tool choreography through agent-driven iterative refinement and semantic error resolution.
• Harnesses a vector database for retrieval-augmented context and troubleshooting proficiency, which is critical for domain-specific error resolution and knowledge integration.
• Enables rapid prototyping and benchmarking across diverse complexity classes, reducing development time and cost.

A plausible implication is that ASIC-Agent’s architecture and associated benchmarking support may inform the development of future autonomous design frameworks, where agentic and LLM integration yields high-quality, reproducible, and efficient ASIC design, potentially democratizing digital hardware development for broader technical audiences.

7. Significance for Autonomous Hardware Design

ASIC-Agent represents a transition from pure code-generation models to integrated agentic systems capable of orchestrating multi-stage hardware design flows. By segmenting complex workflows into expert sub-agents, embedding vector-augmented domain knowledge, and benchmarking against real-world tasks, the system establishes a foundational reference for autonomous ASIC design methodologies. The explicit design and evaluation approach offered by ASIC-Agent and ASIC-Agent-Bench may serve as templates for future research in agent-driven digital design automation, robust benchmarking, and LLM deployment in electronic design domains.