OpenYield: SRAM Yield Analysis Suite

• OpenYield is an open-source benchmark suite defining realistic SRAM models by incorporating second-order parasitic effects, inter-cell leakage, and peripheral variations.
• The framework standardizes yield-analysis evaluation, ensuring reproducible comparisons among diverse rare-event estimators and optimization strategies.
• It supports comprehensive SRAM design tuning, demonstrating significant improvements in noise margins, power consumption, and area while adhering to strict timing constraints.

OpenYield is an open-source benchmark suite for SRAM yield analysis and optimization that is intended to close the gap between simplified academic SRAM models and the industrial realities of modern memory design. It is organized around three components: a realistic SRAM circuit generator, a standardized evaluation platform for yield-analysis algorithms, and a standardized optimization platform for SRAM design tuning. The framework is publicly available at https://github.com/ShenShan123/OpenYield and is positioned as infrastructure for reproducible, industrially relevant SRAM research (Shen et al., 6 Aug 2025).

1. Problem setting and motivation

OpenYield is motivated by two coupled difficulties in SRAM research. The first is the rare-event nature of yield failure. For an array with $N$ cells and per-cell failure probability $P_f$, the standard model is

$Y = (1 - P_f)^N \approx \exp(-N P_f).$

For a $1$ Mb array, achieving $90\%$ yield requires roughly

$P_f < 1.05 \times 10^{-7}.$

This implies that brute-force Monte Carlo can require on the order of $10^9$ or even $10^{10}$ simulations, which the framework treats as infeasible for practical yield estimation (Shen et al., 6 Aug 2025).

The second difficulty is a modeling gap between academic benchmarks and industrial designs. OpenYield reports that, in a review of $45$ recent SRAM yield-analysis papers, over $85\%$ used overly simplified models that omit physical effects that become decisive at advanced nodes. The omitted effects include distributed parasitics on bitlines and wordlines, inter-cell leakage coupling, and peripheral-circuit variation. The framework therefore treats reproducibility not merely as code release, but as agreement on physically realistic benchmark conditions.

This emphasis is tied to the economics of memory design. SRAM is described as the dominant on-chip memory in modern chips and as consuming a very large fraction of die area in AI accelerators and mobile SoCs. Under those conditions, even small yield losses become costly, and inaccuracies in benchmark modeling can invalidate apparent algorithmic advances.

2. Realistic SRAM circuit generation

A central element of OpenYield is a hierarchical SRAM circuit generator implemented in Python and integrated with SPICE-style simulation through PySpice and Xyce. Rather than generating isolated bitcells, it produces complete SRAM netlists that include configurable arrays, wordline drivers, column multiplexers, shared sense amplifiers, precharge and write-driver circuitry, control logic, and the surrounding interconnect structure. The generator supports configurable row and column sizes, focuses primarily on $P_f$0T cells, and includes provisions for $P_f$1T and $P_f$2T-style extensions (Shen et al., 6 Aug 2025).

The framework explicitly incorporates several effects that are stated to be commonly omitted in academic studies.

First, it models second-order parasitic effects using distributed $P_f$3-shaped RC segments for bitlines and wordlines. This produces position-dependent delay and incomplete signal swing along long interconnects. The reported quantitative impact is large: for a $P_f$4-row array, including parasitics increases mean read delay from about $P_f$5 ns to $P_f$6 ns and read power from about $P_f$7 to $P_f$8. This suggests that simplified lumped or cell-only abstractions can distort the effective access path by orders of magnitude rather than by marginal percentages.

Second, it models inter-cell leakage coupling, including subthreshold leakage, gate leakage, and aggregate leakage from many unselected cells on the same bitline or column. The framework emphasizes that this introduces data-pattern dependence into read behavior. In a $P_f$9 example at low supply voltage, leakage changes read delay by around $Y = (1 - P_f)^N \approx \exp(-N P_f).$0 at $Y = (1 - P_f)^N \approx \exp(-N P_f).$1 V, with the effect diminishing at higher $Y = (1 - P_f)^N \approx \exp(-N P_f).$2.

Third, it models peripheral-circuit variation, including sense-amplifier offset voltage, wordline-driver delay and skew, precharge-driver variation, and write-driver voltage and timing variation. Sense-amplifier offset is singled out as particularly important because it directly subtracts from read margin. For a $Y = (1 - P_f)^N \approx \exp(-N P_f).$3 SRAM, including peripherals increases average read power from $Y = (1 - P_f)^N \approx \exp(-N P_f).$4 mW to $Y = (1 - P_f)^N \approx \exp(-N P_f).$5 mW and average write power from $Y = (1 - P_f)^N \approx \exp(-N P_f).$6 mW to $Y = (1 - P_f)^N \approx \exp(-N P_f).$7 mW, while also substantially increasing delay components.

The generator supports the main SRAM failure mechanisms and metrics used in yield studies: read upset via RSNM, write failure via WSNM, hold failure via HSNM, timing and access failure via read and write delays, power consumption, and cell area from DRC rules. OpenYield also describes standard static-noise-margin extraction through butterfly curves, rotated by $Y = (1 - P_f)^N \approx \exp(-N P_f).$8, with the margin defined as the largest embedded square or maximum vertical distance in the butterfly lobes.

3. Standardized evaluation of yield-analysis algorithms

OpenYield provides a common evaluation environment for rare-event yield-analysis methods, with the stated goal of making comparisons fair, transparent, and reproducible. The platform accepts SRAM configuration, technology parameters, design parameters, process-variation statistics, and optimization or analysis goals; it outputs SPICE netlists, yield reports, failure-probability estimates, performance metrics, and, in optimization mode, optimized design parameters. The reported experiments use FreePDK45 with nominal $Y = (1 - P_f)^N \approx \exp(-N P_f).$9 V and model local intra-die random variations as independent Gaussian perturbations applied to each transistor (Shen et al., 6 Aug 2025).

The benchmark includes reference implementations of several baseline algorithms:

Algorithm	Role in OpenYield	Characterization in the benchmark
Standard Monte Carlo (MC)	Unbiased reference baseline	Can be enhanced by stratified sampling and control variates
Mean-Shift Importance Sampling (MNIS)	Rare-event estimator	Shifts the sampling mean toward the most probable failure point
Adaptive Importance Sampling (AIS)	Rare-event estimator	Iteratively refines the proposal distribution
Adaptive Compressed Sampling (ACS)	Rare-event estimator	Uses sparse failure-region representations and compressed sensing ideas
High-dimensional Sparse Compressed Sampling (HSCS)	Rare-event estimator	Targets large parameter spaces with sparse failure regions

The common evaluation discipline is an important part of the framework. Algorithms are compared using the same circuit models, the same SPICE backend, identical variation settings, the same stopping criterion, and comparable simulation budgets. A key termination criterion in the yield experiments is

$1$0

used as the stopping metric for failure-probability estimation.

The platform validates these methods on three benchmark circuits: a single $1$1T cell with $1$2 variation parameters, a $1$3 array with $1$4 parameters, and a $1$5 array with $1$6 parameters. The reported results show that method ranking changes with realism and dimensionality. On the single-cell case, MNIS attains near-MC accuracy with less than $1$7 error and about $1$8 speedup. On the $1$9 case, ACS achieves sub-$90\%$0 error with about $90\%$1 speedup. On the $90\%$2 case, MC requires more than $90\%$3 simulations and about $90\%$4 hours, whereas ACS reaches similar accuracy with only $90\%$5 simulations, about $90\%$6 faster. A plausible implication is that algorithms validated only on low-dimensional bitcell setups may be systematically mis-ranked relative to their behavior on realistic arrays.

4. Optimization platform and objective structure

OpenYield extends beyond yield estimation to standardized SRAM optimization. The platform supports single-objective, multi-objective, and constrained optimization, and the example study uses a $90\%$7T cell in a $90\%$8 array with six design variables: threshold-voltage device types, the widths of pull-down, pull-up, and access transistors, and gate lengths. Widths and lengths range from $90\%$9 to $P_f < 1.05 \times 10^{-7}.$0 nominal in discrete steps (Shen et al., 6 Aug 2025).

A representative constrained optimization problem is given as

$P_f < 1.05 \times 10^{-7}.$1

The associated figure of merit is defined as a logarithmic function of the minimum among HSNM, RSNM, and WSNM, normalized by the maximum of read and write power and by $P_f < 1.05 \times 10^{-7}.$2. In operational terms, the objective promotes larger static-noise margins while penalizing power and area. Timing is enforced separately through the read and write delay constraints.

Five optimizers are implemented: Constrained Bayesian Optimization using Gaussian processes and expected hypervolume improvement, Particle Swarm Optimization, Simulated Annealing, SMAC, and RoSE-Opt. All are run under the same evaluation budget and the same realistic circuit conditions, with each optimization run performing $P_f < 1.05 \times 10^{-7}.$3 SPICE simulations. This design is presented as a way to avoid incomparable reports based on differing circuit abstractions or unequal optimization effort.

The reported optimization outcome using RoSE-Opt is a $P_f < 1.05 \times 10^{-7}.$4 improvement in RSNM, from $P_f < 1.05 \times 10^{-7}.$5 V to $P_f < 1.05 \times 10^{-7}.$6 V, a $P_f < 1.05 \times 10^{-7}.$7 improvement in WSNM, from $P_f < 1.05 \times 10^{-7}.$8 V to $P_f < 1.05 \times 10^{-7}.$9 V, and a $10^9$0 area reduction, from $10^9$1 to $10^9$2, while maintaining the timing constraints. The composite FoM improves from $10^9$3 to $10^9$4. The framework also reports a control study in which designs optimized under simplified models perform poorly when re-evaluated under realistic conditions, sometimes violating timing or losing stability. This is one of the strongest methodological claims associated with OpenYield: optimization quality depends on benchmark realism, not only on optimizer sophistication.

5. Experimental findings and methodological significance

The aggregate experimental evidence in OpenYield supports three general conclusions. First, realistic circuit effects materially change delay, power, and failure behavior. Ignoring parasitics underestimates read delay and power by up to $10^9$5 and $10^9$6, respectively, while omitting peripheral circuits underestimates read delay and power by up to $10^9$7 and $10^9$8. These are not small calibration errors; they alter the physical regime in which a yield-analysis algorithm operates (Shen et al., 6 Aug 2025).

Second, algorithm performance is benchmark-dependent. Some methods perform well on single-cell or low-dimensional cases but degrade sharply as dimensionality and failure-region complexity increase. OpenYield is therefore not only a toolchain but also a standardization mechanism: it makes visible when a method’s apparent advantage is an artifact of an overly easy benchmark.

Third, realistic models are necessary for meaningful optimization. The framework’s control study indicates that design settings found under idealized assumptions can fail when the missing physical effects are restored. In this sense, OpenYield treats circuit realism as part of the optimization problem definition rather than as post hoc validation.

The experiments are conducted in FreePDK45 with nominal $10^9$9 V, Gaussian variation with about $10^{10}$0 sigma for selected parameters, and parallel Xyce simulation. The benchmark suite spans array sizes from $10^{10}$1 to $10^{10}$2 rows, second-order-effect studies for parasitics, leakage, and peripherals, yield-estimation comparisons over parameter dimensions from $10^{10}$3 to $10^{10}$4, and transistor-sizing optimization on a $10^{10}$5T SRAM cell. The authors present the framework as serving a role for SRAM yield research analogous to what ImageNet served for vision or SPEC for computer architecture. This suggests an ambition not merely to publish another simulator, but to define a shared experimental protocol.

6. Scope, limitations, and subsequent use

OpenYield is explicitly described as a first-step ecosystem rather than a complete coverage of SRAM design space. The current release is limited to FreePDK45 and focuses primarily on $10^{10}$6T SRAM cells, although it includes provisions for $10^{10}$7T and $10^{10}$8T-style extensions. These are stated as deliberate design choices rather than accidental omissions. The framework also adopts open-source tools, a Python-based interface, and SPICE-level simulation to balance accessibility with faithful physical validation (Shen et al., 6 Aug 2025).

Its intended use cases include academia-industry collaboration, reproducible comparison of SRAM yield algorithms, benchmarking of machine-learning and surrogate-based rare-event estimators, robust transistor sizing, memory co-design, and eventual extension to advanced nodes and layout-aware analysis and optimization. The emphasis on both analysis and optimization is notable: OpenYield standardizes not only how failure probability is estimated, but also how memory designs are tuned under realistic variation.

A subsequent framework, OpenACMv2, builds specifically on OpenYield for the SRAM portion of approximate digital compute-in-memory design. In that setting, OpenYield provides the variation-aware SRAM optimization backend, including SRAM bank-architecture exploration under fixed capacity, SPICE-based evaluation of candidate organizations, variation- and PVT-aware transistor sizing for $10^{10}$9T bitcells, and reusable single-objective and multi-objective optimization formulations (Zhou et al., 13 Mar 2026). Within OpenACMv2, the reported SRAM results indicate that architecture-level organization dominates the overall PPA tradeoff, while bitcell sizing provides more limited additional gains. This downstream reuse is significant because it shows OpenYield functioning as benchmark infrastructure rather than as a standalone case study.

OpenYield is therefore best understood as a standardized, realism-oriented experimental substrate for SRAM yield research. Its defining contribution is to make industrially important second-order effects, reproducible algorithm comparison, and optimization under shared circuit conditions part of the same benchmarked problem.