ListenToJESD204B: Lightweight FPGA Receiver

• ListenToJESD204B is an open-source, lightweight JESD204B receiver IP core for FPGA ultrasound systems, enabling scalable high-throughput acquisition.
• Its modular implementation integrates octet alignment, elastic buffering, and optional descrambling to produce cycle-accurate AXI-Stream output.
• The design achieves deterministic Subclass 1 operation with significantly reduced FPGA resource usage, validated through both simulation and hardware testing.

Searching arXiv for the specified papers and closely related context. I’ll look up the target paper and a contextual JESD204B/TES paper on arXiv to ground the article in current literature. ListenToJESD204B is an open-source, lightweight JESD204B receive IP core for FPGA-based ultrasound acquisition systems, introduced as a practical alternative to LVDS links and proprietary vendor JESD IP in settings that require hundreds of tightly synchronized channels, tens of MSPS sampling rates, and strict timing alignment. Implemented in synthesizable SystemVerilog for AMD Xilinx Zynq UltraScale+ devices, it targets Subclass 1 receive operation, provides cycle-accurate AXI-Stream-compatible output, and is designed to minimize FPGA resource consumption while preserving deterministic latency and protocol compliance (Bhattacharjee et al., 20 Aug 2025).

1. Problem setting and design rationale

The core is motivated by the scaling limits of conventional LVDS in high-channel-count ultrasound systems. In the reported framing, many ADCs operate at tens of MSPS with 16-bit resolution, so aggregate throughput becomes too large for parallel LVDS interfaces. The cited limitations are bandwidth, FPGA pin count, signal-integrity and routing difficulty at high speeds, and the complexity of synchronizing many converters. JESD204B is presented as the appropriate replacement because it uses serial high-speed lanes, scales to many channels, provides deterministic latency, and standardizes the high-speed ADC interface (Bhattacharjee et al., 20 Aug 2025).

ListenToJESD204B is positioned against commercial JESD204B IP cores that are described as proprietary, expensive, and resource-intensive. Its stated design goals are lightweight resource usage, open-source permissive licensing under Solderpad 0.51, deterministic JESD204B Subclass 1 latency, and compatibility with AMD Xilinx Zynq UltraScale+ devices, specifically ZU19EG. The emphasis on fabric efficiency is tied directly to downstream workloads such as compression, beamforming, and reconstruction, which compete for the same FPGA resources (Bhattacharjee et al., 20 Aug 2025).

A broader 2025 trend is consistent with this motivation: JESD204B is also used in room-temperature TES readout electronics to replace wide parallel ADC-to-FPGA interfaces, reducing PCB area and wiring complexity while sustaining high data throughput for multiplexed detector systems. This suggests that ListenToJESD204B belongs to a wider class of architectures in which serialized converter links are adopted primarily for scalability, physical compactness, and interface simplification rather than only for raw bandwidth (Li et al., 11 Jan 2025).

2. Receiver architecture and data path

The implementation is modular. At the top level, the receiver accepts JESD204B streams from the PHY and emits AXI-Stream-compatible parallel data into the FPGA fabric. The architecture comprises a per-lane data_path module, a control FSM for link bring-up, octet alignment logic, optional descrambling, SYSREF-synchronized LMFC generation, and per-lane elastic buffers with a coordinated release mechanism (Bhattacharjee et al., 20 Aug 2025).

Each lane processes four 8-bit octets per cycle. The lane-level pipeline registers incoming data, performs Code Group Synchronization, validates the Initial Lane Alignment Sequence, optionally descrambles payload data, and then aligns lane data through an elastic buffer. After lane-local processing, the top-level receiver merges the lane outputs and drives an AXI-Stream-like interface with rx_valid. The design explicitly assumes continuous downstream consumption and does not implement tready backpressure. In context, this choice is used to keep the interface simple and lightweight rather than to provide a fully general streaming contract (Bhattacharjee et al., 20 Aug 2025).

Octet alignment is handled in a dedicated octet_align block. Incoming 10-bit symbols from the transceivers are first decoded and then byte-aligned by detecting the /K28.5/ comma character and rotating the received words to restore proper byte framing. This function is structurally important because CGS, ILAS, and payload interpretation all depend on correct octet boundaries (Bhattacharjee et al., 20 Aug 2025).

The optional payload descrambler is LFSR-based and uses the polynomial

$G(x) = x^{14} + x^{13} + 1$

in a 32-bit-wide pipelined form. The ability to enable or disable descrambling by RTL parameter is presented as a compatibility mechanism: systems with scrambling enabled can restore original data before output, while systems that do not use scrambling can avoid unnecessary logic (Bhattacharjee et al., 20 Aug 2025).

3. Link bring-up, Subclass 1 timing, and deterministic latency

The link initialization FSM is described with five states: ST_RESET, ST_WAIT_FOR_PHY, ST_CGS, ST_ILAS, and ST_SYNCED. ST_RESET performs internal reset and initialization; ST_WAIT_FOR_PHY waits for transceiver readiness; ST_CGS monitors the comma sequence, especially /K28.5/, and asserts SYNC to align the transmitter; ST_ILAS verifies the multiframe configuration sequence and checks link parameters; and ST_SYNCED corresponds to normal payload reception. The FSM uses a stability flag and a cycle counter so that transient conditions do not spuriously advance the state, and misalignment or faults can force the link back to CGS (Bhattacharjee et al., 20 Aug 2025).

Subclass 1 deterministic latency is realized through SYSREF-locked LMFC generation and LMFC-aligned lane release. The LMFC resets on SYSREF edges and rolls over every

$F \times K$

octets, where $F$ is the number of octets per frame and $K$ is the number of frames per multiframe. In the paper’s interpretation, this repeatable multiframe timing is the central mechanism by which startup and reset behavior become deterministic (Bhattacharjee et al., 20 Aug 2025).

Each lane contains a circular elastic buffer implemented as a FIFO. A centralized buffer_release controller monitors readiness across lanes and releases data only when all buffers are ready, so lane outputs become synchronized. The stated contribution of this structure is threefold: deterministic LMFC-aligned release, skew tolerance for hardware links that do not arrive perfectly aligned, and scalability through per-lane rather than globally coupled buffering (Bhattacharjee et al., 20 Aug 2025).

A recurring misconception in discussions of lightweight serial-link IP is that low logic cost necessarily precludes deterministic timing. The reported design directly counters that assumption by making deterministic Subclass 1 behavior a first-class design goal and by coupling SYSREF, LMFC generation, and coordinated elastic-buffer release to produce cycle-accurate AXI-Stream output after synchronization (Bhattacharjee et al., 20 Aug 2025).

4. Supported operating envelope and implementation profile

The reported supported configuration is receive-only JESD204B Subclass 1 on AMD Xilinx Zynq UltraScale+, targeting ZU19EG. The user-oriented top-level wrapper supports up to 4 lanes per link, while the underlying modules are described as compatible with up to 32 lanes per link. The lane rate spans 6 Gb/s to 12.8 Gb/s, the datapath width is 32 bits, and supported frame parameters are $F=4$–$32$ octets per frame and $K=1$–$32$ frames per multiframe (Bhattacharjee et al., 20 Aug 2025).

Resource utilization is a central result because the core is explicitly intended to preserve logic for ultrasound processing. For the reported two-channel implementation, the paper gives the following synthesis figures:

Metric	ListenToJESD204B	Xilinx JESD204C IP
CLB LUTs	437 with descrambling, 426 without	2092
CLB Registers	429 with descrambling, 410 without	1988
CLBs	107 with descrambling, 102 without	470

These numbers are the basis of the reported reduction of roughly 79% in logic usage relative to the vendor reference. The paper also reports timing closure at $320\ \text{MHz}$ with a worst negative slack of $0.31\ \text{ns}$ as part of the synthesis discussion (Bhattacharjee et al., 20 Aug 2025).

Startup behavior is also quantified. The receiver has a fixed startup latency of 13 clock cycles, approximately 40 ns, before the first valid sample appears, and its throughput after startup is stated to match the Xilinx JESD204C IP. In context, this combination of fixed startup delay and matched steady-state throughput is important because many acquisition systems care about both repeatability and sustained payload rate (Bhattacharjee et al., 20 Aug 2025).

5. Verification and hardware validation

Validation is performed in both simulation and hardware. The simulation environment is derived from Xilinx’s JESD204C example design but configured to emulate JESD204B mode. ListenToJESD204B is inserted as the device under test, while the Xilinx JESD204C IP operating in B-mode serves as transmitter and reference. The transmitter and receiver are configured with matched $F \times K$0 and $F \times K$1, and the test vectors include CGS, ILAS, and randomized payloads. Assertions check correct FSM transitions, ILAS extraction, multiframe alignment, and output correctness against a golden reference (Bhattacharjee et al., 20 Aug 2025).

Hardware validation uses a Xilinx Zynq UltraScale+ ZU19EG, TI AFE58JD48 analog front-ends, an LMK04826B clock conditioner for SYSREF, a 5 MHz, 32-channel ultrasound transducer, and ILA/JTAG-based inspection. In this setup, the AFE operates at 80 MSPS with 16-bit resolution and streams over two JESD204B links at 12.8 Gb/s (Bhattacharjee et al., 20 Aug 2025).

The reported hardware results are specific. Digital ramp-pattern reception works correctly; lane synchronization is achieved within 15 frame clock cycles from initialization; a 5 MHz sine wave is reconstructed correctly in both scrambled and descrambled modes; and a real ultrasound phantom acquisition is demonstrated successfully. Long-term stability is verified through 30 minutes of continuous streaming with no invalid frames or errors. The abstract gives a closely related statement: block stability was verified by streaming 80 MSPS, 16-bit samples over two 12.8 Gb/s links for 30 minutes with no errors (Bhattacharjee et al., 20 Aug 2025).

A second common misconception is that an open-source serial-link receiver is necessarily less verifiable than proprietary vendor IP. The reported methodology suggests the opposite is at least plausible in this case: the design is checked both against a vendor reference in simulation and against real ADC hardware under sustained streaming conditions (Bhattacharjee et al., 20 Aug 2025).

6. System integration, scope, and relation to other JESD204B deployments

ListenToJESD204B is situated inside an open ultrasound front-end for a 256-channel system consisting of 16 AFEs with 16 channels each. The total data rate is described as approximately 327 Gb/s, with ADC data entering the ZU19EG fabric through 32 JESD lanes. The received stream is immediately compressed, reducing outbound bandwidth to about 70 Gb/s, which is stated to fit within a 100 Gb Ethernet link for RDMA/GPU processing or NVMe storage (Bhattacharjee et al., 20 Aug 2025).

Within this system framing, the core’s low resource usage is not an isolated optimization but part of a broader architecture. The intended consequence is that FPGA resources remain available for compression, beamforming, real-time reconstruction, and other ultrasound processing blocks. This suggests that the design should be understood less as a standalone protocol endpoint than as an enabling infrastructure component in larger real-time imaging pipelines (Bhattacharjee et al., 20 Aug 2025).

Its scope is nevertheless specific. The paper describes a receive-only JESD204B Subclass 1 core targeting AMD Xilinx Zynq UltraScale+ devices, with a user-friendly wrapper up to 4 lanes per link and lower-level compatibility up to 32 lanes. It does not present itself as a universal, feature-complete replacement for all vendor JESD offerings; rather, it trades some vendor-IP conveniences for transparency, reproducibility, and reduced logic footprint (Bhattacharjee et al., 20 Aug 2025).

The wider significance of this trade-off is reinforced by contemporaneous JESD204B adoption in other instrumentation domains. In TES room-temperature readout electronics, JESD204B is used to move digitized ADC data from an 8-channel converter board to FPGA processing while reducing board count and physical footprint relative to parallel interfaces. In that case, the serialized link supports a compact architecture for large multiplexed detector arrays and real-time multi-gigabit streaming (Li et al., 11 Jan 2025). Taken together, these reports indicate that JESD204B’s value in modern acquisition systems is not limited to nominal line rate; it also resides in deterministic timing, reduced pin count, board-level compaction, and scalable converter integration.

7. Significance and interpretation

The central technical identity of ListenToJESD204B is the conjunction of four properties stated explicitly in the source: deterministic JESD204B Subclass 1 timing, very small FPGA resource usage, open-source permissive licensing, and validated operation on real ultrasound hardware (Bhattacharjee et al., 20 Aug 2025). Its architecture realizes these properties through a restrained receive pipeline—CGS and ILAS handling, optional 32-bit-wide pipelined descrambling, SYSREF-locked LMFC generation, and coordinated elastic buffering—rather than through a broad feature surface.

For research environments, reproducibility is a major part of the contribution. Release under the Solderpad 0.51 license, implementation in synthesizable SystemVerilog, and compatibility with widely used UltraScale+ infrastructure make the design suitable for open hardware workflows and for studies in which downstream imaging or compression logic must coexist with the transport layer on a shared device (Bhattacharjee et al., 20 Aug 2025).

A plausible implication is that the core is especially relevant where deterministic sample timing is operationally inseparable from algorithmic performance, as in beamforming and time-aligned acquisition. The paper’s combination of fixed startup latency, cycle-accurate output, and sustained error-free hardware streaming is consistent with that interpretation. In this sense, ListenToJESD204B is best understood as a specialized but rigorously scoped JESD204B receiver whose importance lies in making deterministic multi-lane acquisition more accessible within open and resource-constrained FPGA ultrasound systems (Bhattacharjee et al., 20 Aug 2025).