Hierarchical Logical Processor (HLP)

• The Hierarchical Logical Processor (HLP) is a concatenated quantum fault-tolerance architecture that merges high-rate CSS codes with rotated surface codes for enhanced encoding efficiency.
• HLP employs a hierarchical structure using cores and shuttle buses to implement transversal hybrid-unit CNOT gates and a two-tier syndrome extraction strategy that minimizes non-local operability.
• Benchmarks show that HLP can achieve up to 3–4× higher qubit efficiency with reduced space overhead and improved logical measurement parallelism, despite longer level-1 round times.

Searching arXiv for the cited HLP-related papers to ground the article in current preprints. Looking up arXiv entries for "Hierarchical Logical Processor" and related hierarchical parallelism formulations. The Hierarchical Logical Processor (HLP) is a concatenated fault-tolerance architecture for quantum computation that combines a high-rate quantum CSS code with the rotated surface code (RSC) in order to obtain beyond-RSC encoding efficiency while requiring long-range connectivity only once every $\Theta(d_0)$ rounds of level-0 error correction, where $d_0$ is the base-code distance (Chen et al., 21 Jun 2026). In this construction, the high-rate code appears at level 1, while each level-1 qubit is itself encoded into a distance-$d_0$ RSC patch at level 0. The central architectural objective is to preserve the attractive locality and threshold properties of the RSC while amortizing the cost of the non-local couplings that direct implementations of qLDPC-like codes would otherwise require in every syndrome-extraction round (Chen et al., 21 Jun 2026).

1. Definition and architectural objective

HLP is designed to reconcile two fault-tolerance regimes that are usually in tension. Standard RSCs are experimentally friendly because they use local stabilizer patterns and have a high threshold, but a distance-$d$ RSC encodes one qubit in $d^2$ physical qubits. Direct implementations of qLDPC codes can improve encoding rate substantially, but they generally require non-local couplings in every round of syndrome extraction, which increases physical error exposure and scheduling complexity on hardware such as neutral-atom arrays (Chen et al., 21 Jun 2026).

The HLP construction addresses this by placing a level-1 high-rate quantum CSS code, denoted $\mathcal C_1$, on top of a level-0 RSC. Each logical qubit of $\mathcal C_1$ is therefore realized not as a raw physical qubit, but as a small RSC patch. This means that the physical machine is assembled from RSC “working units,” with high-rate coding imposed only at the logical layer. The architectural compromise is explicit: HLP aims to achieve beyond-RSC encoding efficiency without paying the operational price of long-range gates in every error-correction cycle (Chen et al., 21 Jun 2026).

A common source of confusion is the acronym itself. In the quadruped-locomotion literature, “HLP” denotes a high-level policy rather than a logical processor. In that setting, the HLP selects footstep placement goals for a low-level policy and performs online optimization over a learned value function without additional RL training or environment samples (Coholich et al., 24 Jun 2025). That use of the acronym is unrelated to the quantum fault-tolerance architecture.

2. Constituent working units and concatenated code structure

At the physical-layout level, HLP is built from two types of RSC-based working units: cores and shuttle buses (Chen et al., 21 Jun 2026).

Working unit	Geometry	Level-1 role
Core	Ordinary distance-$d_0$ RSC patch	Data qubit
Shuttle bus	Elongated RSC patch of width $d_0$ and length $d_0 d_1$	Ancilla
Level-1 code $d_0$0	Distance $d_0$1	Outer CSS code

The level-1 code $d_0$2 has distance $d_0$3, and the total concatenated code distance is effectively $d_0$4. The elongation of the shuttle bus is functionally essential: a bus is long enough to couple transversally to multiple cores while preserving a surface-code-like patch layout. The paper distinguishes between an $d_0$5 bus and a $d_0$6 bus according to whether the logical $d_0$7 or logical $d_0$8 operator runs along the long edge (Chen et al., 21 Jun 2026).

This geometry is the mechanism by which HLP obtains beyond-planar connectivity without abandoning a 2D patch-based organization. The underlying architecture remains composed of RSC patches, but logical couplings between patches are no longer confined to nearest-neighbor interactions in a planar graph. A plausible implication is that the “hierarchical” character of HLP is not merely code concatenation; it is also a physical-organization principle in which level-0 locality is retained while level-1 non-locality is selectively exposed.

3. Hybrid-unit CNOTs and two-tier syndrome extraction

The key operation that makes HLP practical is the transversal hybrid-unit CNOT gate. A hybrid-unit CNOT is a depth-1 layer of physical CNOTs that implements a logical CNOT between one shuttle bus and up to $d_0$9 cores simultaneously (Chen et al., 21 Jun 2026). Two variants are specified. In bus-core CNOTs, an $d_0$0 bus acts as control and multiple cores are targets. In core-bus CNOTs, multiple cores act as controls and a $d_0$1 bus is the target (Chen et al., 21 Jun 2026).

Syndrome extraction is correspondingly two-tiered. At level 0, every core and shuttle bus runs standard RSC syndrome extraction continuously. At level 1, stabilizers of $d_0$2 are measured using readout gadgets assembled from shuttle buses and hybrid-unit CNOTs. An $d_0$3-basis readout gadget initializes an $d_0$4 bus, applies a sequence of core-bus or bus-core CNOTs so that each support qubit is touched exactly once, and then measures the bus; the $d_0$5-basis version is analogous (Chen et al., 21 Jun 2026).

The cadence of non-local operations is a defining design parameter. Adjacent hybrid-unit CNOTs are separated by at least $d_0$6 level-0 rounds, and adjacent readout gadgets are separated by at least $d_0$7 rounds. The preferred setting for the main constructions is $d_0$8 and $d_0$9, with long-range CNOT layers therefore needed only once per $d$0 level-0 rounds for each working unit (Chen et al., 21 Jun 2026). This schedule is not just an implementation detail: it is the principal means by which HLP reduces both accumulated error from repeated non-local operations and the routing burden associated with beyond-planar connectivity.

4. Error model, scaling relations, and logical measurements

Under a phenomenological depolarizing noise model, the residual level-0 error after decoding behaves like a local stochastic level-1 error model, except for a rare event whose probability is exponentially suppressed in $d$1, roughly $d$2 (Chen et al., 21 Jun 2026). The induced effective level-1 error rate scales as

$d$3

This relation is central to the paper’s argument that amortized long-range connectivity can still yield a well-controlled effective code.

For logical operations, HLP is particularly optimized for highly parallel logical Pauli measurements. The architecture introduces a logical measurement sequence (LMS), defined as a chain of $d$4 logical readout gadgets embedded in $d$5 consecutive level-1 syndrome-extraction rounds. This repetition gives full level-1 distance for measuring a logical $d$6 or $d$7 operator (Chen et al., 21 Jun 2026). LMSs for different commuting logical operators can be densely packed, with gadgets from different LMSs separated by as little as one level-0 round. The paper proves that this arrangement still supports fault-tolerant decoding (Chen et al., 21 Jun 2026).

The framework also extends to general logical Pauli measurements via $d$8-transformed and $d$9-transformed readout gadgets. These permit measurement of arbitrary logical Pauli operators $d^2$0, including the $d^2$1 case, without requiring a catalytic logical $d^2$2 state (Chen et al., 21 Jun 2026). In addition, HLP supports interfacing with external RSC patches through extended hybrid-unit CNOTs, enabling joint measurements across an HLP and outside logical qubits (Chen et al., 21 Jun 2026).

Several caveats accompany these scaling claims. The ideal logical measurement error for an LMS scales like $d^2$3, whereas the rigorous worst-case bound obtained through separate level-0 and level-1 analyses scales like $d^2$4. The paper explicitly attributes this gap to proof technique rather than necessarily to the architecture itself, and circuit-level simulations suggest performance close to full distance (Chen et al., 21 Jun 2026).

5. Benchmarks, overheads, and trade-offs

The paper reports circuit-level simulations for several concrete HLP constructions (Chen et al., 21 Jun 2026). For an HLP based on the $d^2$5 Iceberg code, level-1 $d^2$6 and $d^2$7 stabilizers are extracted sequentially, and the logical error rate decreases with core distance at nearly twice the rate of the RSC baseline. For the $d^2$8 Square Berg code, multiple concurrent shuttle buses are used to extract level-1 stabilizers in parallel, yielding another substantial improvement (Chen et al., 21 Jun 2026).

The most detailed benchmark concerns an HLP based on the $d^2$9 code. At a physical error rate of $\mathcal C_1$0, this construction achieves roughly $\mathcal C_1$1 to $\mathcal C_1$2 higher qubit efficiency than the standard RSC over target logical error rates from $\mathcal C_1$3 to $\mathcal C_1$4 (Chen et al., 21 Jun 2026). Relative to the yoked surface code built from the same level-1 code, the HLP reduces space overhead by about 100–200 physical qubits per logical qubit and shortens the logical error-correction cycle time by a factor of 20–30 (Chen et al., 21 Jun 2026).

These gains are paired with explicit trade-offs. Even the $\mathcal C_1$5 HLP still has a level-1 round time about ten times longer than the bare RSC baseline (Chen et al., 21 Jun 2026). The architecture therefore exchanges latency for higher encoding efficiency and for the ability to perform highly parallel logical measurements. A plausible implication is that HLP is most attractive in regimes where qubit efficiency and measurement parallelism dominate raw cycle-time minimization.

6. Assumptions, limitations, and broader conceptual context

The main analysis assumes perfect time boundaries and imposes schedule-spacing constraints such as $\mathcal C_1$6, $\mathcal C_1$7, and, for $\mathcal C_1$8-gadgets, $\mathcal C_1$9 (Chen et al., 21 Jun 2026). The paper notes that these restrictions are partly for analytical cleanliness rather than hard architectural limits, and that practical hardware may admit more flexible scheduling (Chen et al., 21 Jun 2026). This qualification is important because the main performance and fault-tolerance arguments depend on the infrequent appearance of potentially correlated long-range gates.

The broader conceptual significance of the term “Hierarchical Logical Processor” extends beyond this specific FTQC architecture. In programming-model research, “Generalizing Hierarchical Parallelism” proposes a hierarchy of logical execution resources exposed to the programmer, where nested constructs map logical levels to physical hardware levels using clauses such as level, sync, reserve, bind_ancestor, and hierarchical map (Kruse, 2023). That work is described as “very close in spirit to a Hierarchical Logical Processor (HLP) model,” in which logical processors form a tree, each level has capabilities and communication properties, and nested program regions map onto sub-hierarchies (Kruse, 2023).

This suggests a cross-domain pattern in the use of the term. In the quantum-computing sense, HLP denotes a hierarchical logical architecture built from RSC patches and shuttle buses. In the OpenMP-oriented sense, it denotes a hierarchy of logical execution resources. The shared theme is a structured decomposition into levels with distinct roles and capabilities, but the technical objects are different: concatenated code patches and syndrome-extraction schedules in one case, execution hierarchy and capability-based mapping in the other.