ZX Interleaving Syndrome Extraction

• ZX interleaving syndrome extraction is a quantum error correction technique that interleaves Z- and X-stabilizer measurements to mitigate hook errors while preserving full fault distance.
• It utilizes spacetime tile motion and an interleaved CNOT scheduling to achieve a minimum-depth, four-layer circuit in both surface-code and qLDPC settings.
• Numerical studies show that this method retains the full nominal fault distance and significantly reduces circuit depth compared to non-interleaved approaches.

Searching arXiv for the named topic and closely related work to ground the article in current papers. ZX interleaving syndrome extraction denotes a class of syndrome-extraction constructions in which $Z$- and $X$-stabilizer measurements are deliberately interleaved, rather than compiled or executed as strictly separated subroutines. In the surface-code setting, the term refers to a minimum-depth, distance-preserving schedule for arbitrary regular tile layouts that neutralizes hook-error shortcuts in the decoding graph while retaining four CNOT layers per round (Hirai et al., 2 Mar 2026). In a broader qLDPC setting, closely related interleaving principles appear as global scheduling rules for $\mathrm{CX}$ and $\mathrm{CZ}$ gates, where logically equivalent $X$- and $Z$-type subroutines may cross subject to an even-parity commutativity condition, enabling depth-optimal or near-optimal syndrome extraction for arbitrary stabilizer families (Zhang et al., 23 Mar 2026).

1. Problem setting and motivation

Syndrome extraction is the circuit process by which all stabilizer generators are measured round by round. The central obstacle motivating ZX interleaving is the hook error: a single fault on a measurement qubit can propagate through the CNOT schedule to multiple data qubits and thereby create shortcut paths in the decoding graph. In the rotated surface code, the relevant distinction is between code distance, identified with the patch side length $d$, and fault distance, defined as “the minimum number of physical errors in the circuit required to cause logical errors.” Hook-error propagation can reduce the fault distance below $d$ even when the code distance is unchanged (Hirai et al., 2 Mar 2026).

The standard example is a $Z$-stabilizer measurement circuit in which an error on the measurement qubit after the first two CNOTs spreads to two data qubits, because a CNOT copies a $Z$ error from the target to the controls. If the resulting correlated data error aligns with a logical operator, a logical failure can arise with fewer faults than the nominal distance. For memory layouts, carefully chosen CNOT orderings can orient hook propagation perpendicular to the logical operator, but this ceases to be sufficient for more general layouts such as lattice surgery unless the schedule itself is redesigned (Hirai et al., 2 Mar 2026).

This establishes the technical niche of ZX interleaving: it is not merely a depth optimization, but a method for reshaping error propagation in spacetime so that minimum-depth syndrome extraction remains compatible with full circuit-level distance.

2. Surface-code construction and interleaving patterns

The surface-code construction considers regular tile layouts, meaning square, tile-like stabilizers together with appropriate two-qubit boundary stabilizers. The standard rotated-surface-code memory circuit already admits a minimum-depth schedule with four layers of CNOT gates, classically associated with the N-shaped ordering for $X$0 stabilizers and Z-shaped ordering for $X$1 stabilizers. ZX interleaving keeps the same four-layer depth target but replaces the usual orientation rule by an interleaving rule derived from tile motion in spacetime (Hirai et al., 2 Mar 2026).

Two patterns are central. The first, inherited from the memory-layout construction discussed in relation to McEwen et al. (2023), is

$X$2

meaning that $X$3 tiles move toward the $X$4 boundary and $X$5 tiles move toward the $X$6 boundary. The paper describes this as a new ordering, neither N-shaped nor Z-shaped, but still depth-4. The second pattern is the generalization needed for arbitrary layouts: $X$7 Here $X$8 tiles move toward the $X$9 boundary and $\mathrm{CX}$0 tiles move toward the $\mathrm{CX}$1 boundary. This additional pattern is required for layouts such as logical Pauli-$\mathrm{CX}$2 measurement via lattice surgery, where boundary connectivity differs from the memory case. It uses extra measurement qubits only on the boundaries, but preserves the same minimum CNOT depth and the same full-distance objective (Hirai et al., 2 Mar 2026).

The design requirements stated for the construction are unusually strict: a simple rule for determining CNOT order from the layout, fault distance equal to code distance for any regular tiling, and no increase in syndrome-extraction round length. The paper argues that existing approaches satisfy at most two of these simultaneously. ZX interleaving is presented as the construction that satisfies all three for arbitrary regular surface-code layouts (Hirai et al., 2 Mar 2026).

3. Decoding-graph mechanism and distance preservation

The decoding-graph interpretation is the conceptual core of ZX interleaving syndrome extraction. In this picture, detectors are graph nodes, graphlike errors are edges, and hook errors appear as shortcut edges spanning across a tile. The fault distance is then the minimum number of edges required to connect opposite logical boundaries. The logical-boundary criterion is stated explicitly: “an error chain that connects the two distinct Z (X) walls works as a logical Pauli Z (X) error.” Full fault distance therefore requires the decoding-graph distance between same-color walls to be at least $\mathrm{CX}$3 (Hirai et al., 2 Mar 2026).

ZX interleaving changes the spacetime geometry of the graph. The key claim is that hook-error edges are shortened because tiles move parallel to the hook direction but in the opposite direction. In the paper’s phrasing, such hook errors become “harmless regardless of their direction” and “effectively, they no longer exist.” This is the mechanism by which a four-layer circuit can preserve the full fault distance for arbitrary regular layouts, rather than only for specially oriented memory patches (Hirai et al., 2 Mar 2026).

The numerical distance results are correspondingly sharp. For memory experiments, the reported fault distances are: hook-avoiding N/Z ordering at $\mathrm{CX}$4, hook-prone N/Z ordering at $\mathrm{CX}$5, alternating ordering at $\mathrm{CX}$6, and both ZX interleaving variants at $\mathrm{CX}$7. For lattice-surgery $\mathrm{CX}$8 measurement, all methods preserve full fault distance for $\mathrm{CX}$9 errors, but for $\mathrm{CZ}$0 errors the asymmetry is pronounced: N/Z ordering gives $\mathrm{CZ}$1, alternating gives $\mathrm{CZ}$2, and ZX interleaving gives $\mathrm{CZ}$3. The paper identifies this as one of its strongest results, because it isolates the layout regime in which minimum depth and full fault distance were previously not achieved together (Hirai et al., 2 Mar 2026).

A plausible implication is that ZX interleaving should be understood less as a local CNOT-ordering trick than as a graph-engineering method: it operates by modifying the detector geometry so that the dangerous low-weight homologically nontrivial paths never materialize.

4. Circuit structure, hardware constraints, and performance trade-offs

The surface-code schedule preserves the standard minimum-depth rhythm of repeated rounds built from reset $\mathrm{CZ}$4, Hadamard $\mathrm{CZ}$5 on selected measurement qubits, four CNOT layers, a final Hadamard stage, and measurement $\mathrm{CZ}$6. The method explicitly avoids simultaneous execution of measurements or resets with CNOTs, a point emphasized in contrast to prior proposals whose minimum-depth claims depend on such concurrency. An additional implementation detail is that each physical qubit needs coupling to only three neighboring data qubits, in the same hexagonal-grid style associated with McEwen et al. (Hirai et al., 2 Mar 2026).

The decoding analysis is verified numerically using Stim’s shortest_graphlike_error as an upper bound on fault distance and search_for_undetectable_logical_errors to confirm the exact distance. Under circuit-level depolarizing noise, with one-qubit depolarizing noise after each 1-qubit gate and two-qubit depolarizing noise after each 2-qubit gate, decoding is performed with PyMatching and Monte Carlo sampling with Sinter. The experiments cover both memory runs with $\mathrm{CZ}$7 rounds and logical Pauli-$\mathrm{CZ}$8 measurements via lattice surgery (Hirai et al., 2 Mar 2026).

The logical-error behavior exhibits a nontrivial trade-off. In the low-noise regime, ZX interleaving behaves similarly to the best full-distance implementations in memory experiments and can outperform alternating ordering. However, the interleaving variants introduce additional error events from measurement errors and tile movement, and the threshold is therefore slightly lower than in competing methods, including even the hook-prone N/Z schedule in one variant. The paper reports a crossover: at low physical error rates, ZX interleaving can outperform alternating ordering, whereas at higher physical error rates or larger code distances, alternating ordering can have lower logical error rate (Hirai et al., 2 Mar 2026).

This trade-off limits any overly simple identification of full fault distance with uniformly superior logical performance. ZX interleaving guarantees the former at minimum depth for arbitrary regular layouts, but its finite-noise performance remains schedule-dependent.

5. Generalization to arbitrary qLDPC codes

A broader form of ZX interleaving appears in the compilation framework Auto-Stabilizer-Check (ASC), where syndrome extraction for a general qLDPC code is treated as a global scheduling problem over all stabilizer checks, rather than as two separately compiled $\mathrm{CZ}$9-only and $X$0-only circuits. The code is represented in binary symplectic form by an $X$1 check matrix $X$2. Ancilla $X$3 must interact with data qubit $X$4 whenever $X$5 or $X$6, corresponding to an $X$7-type or $X$8-type incidence in the stabilizer generator. The resulting circuit consists of $X$9 and $Z$0 gates, together with ancilla preparation and final measurement, and the optimization target is the two-qubit circuit depth in TICKs, where each TICK permits each qubit to participate in at most one two-qubit gate (Zhang et al., 23 Mar 2026).

The essential interleaving rule is a commutativity proposition. $Z$1- and $Z$2-stabilizer measurement subroutines need not be compiled in a rigid “all $Z$3 first, then all $Z$4” order. Instead, the compiler may interleave them whenever the parity of the inversion number in the $Z$5-$Z$6 order over shared data qubits is even. Equivalently, the circuit remains correct when the relative order of shared $Z$7 and $Z$8 gates is swapped an even number of times. This is the formal mechanism by which ASC exploits ZX interleaving to beat naive separated scheduling (Zhang et al., 23 Mar 2026).

The optimization objective is

$Z$9

where $d$0 is the TICK at which ancilla $d$1 interacts with data qubit $d$2. ASC converts this to bounded satisfiability by imposing

$d$3

together with unique-qubit-occupancy, unique-ancilla-occupancy, exact-check-completion, and even-parity commutativity constraints. The search starts at the lower bound $d$4, the maximum degree of the Tanner graph, and increases $d$5 up to $d$6, returning an optimal schedule upon satisfiability and a near-optimal schedule in the presence of solver timeouts (Zhang et al., 23 Mar 2026).

The reported compilation results are substantial. For IBM’s bivariate bicycle codes, ASC generates depth-7 syndrome-extraction circuits for all reported instances and certifies that no depth-6 circuit exists for those examples, resolving an open question from IBM’s work. Examples including $d$7, $d$8, $d$9, $d$0, $d$1, $d$2, and $d$3 all compile to depth 7, while ASAP gives depth 15–16 and coloration-based scheduling gives depth 12. Across the benchmark set, ASC reduces circuit depth by roughly 50% and achieves about a $d$4–$d$5 suppression of logical error rate under circuit-level depolarizing noise with Stim and BP-OSD decoding (Zhang et al., 23 Mar 2026).

This suggests that the surface-code notion of ZX interleaving, originally expressed through tile motion and hook-error shortening, has a natural abstraction as a global parity-constrained crossing rule between $d$6- and $d$7-type measurement subroutines.

6. Related interpretations, misconceptions, and alternative design philosophies

A common misconception is to equate “ZX interleaving” with ZX-calculus rewriting. The two are related only indirectly. In the surface-code construction, “ZX” refers to interleaving $d$8- and $d$9-stabilizer tiles or subroutines in spacetime. By contrast, a separate circuit-centric line of work studies detector-aware rewrites of phase-free ZX diagrams while preserving MWPM-decodability. There the central object is a detector basis of Pauli webs, and matchability is defined by the sparsity condition

$Z$0

Rewrites such as $Z$1, $Z$2, $Z$3, and generalized $Z$4, $Z$5, $Z$6 are shown to preserve this property, enabling extraction of efficiently decodable fault-tolerant syndrome-extraction circuits from CSS matchable, phase-free ZX diagrams (Schweikart et al., 19 Mar 2026).

A second misconception is that interleaving is always the preferred design principle. A contrasting framework based on left-right circuits deliberately avoids interleaving gates. It defines non-interleaved circuits as schedules in which either all overlapping $Z$7-type CNOTs precede all overlapping $Z$8-type CNOTs or vice versa, and uses a left/right partition of the parity-check matrices to create two staggered CNOT blocks. That framework emphasizes low depth, low ancilla idling, and explicit residual-error analysis. It proves that for the gross code $Z$9, no non-interleaving syndrome-extraction circuit can reach circuit distance 12, and it identifies an explicit circuit conjectured to achieve distance 11. At the same time, it states that an interleaved version obtained by changing timing while preserving internal order cannot decrease circuit distance and may increase it (Strikis et al., 5 Mar 2026).

Taken together, these works locate ZX interleaving syndrome extraction within a broader design landscape. One branch uses interleaving to preserve full fault distance at minimum depth for arbitrary regular surface-code layouts; another lifts the same intuition to global qLDPC compilation through commutativity-constrained scheduling; and a third studies when interleaving should be avoided in favor of analyzable non-interleaved constructions. The resulting picture is not a single algorithmic recipe but a family of methods for controlling hook propagation, decoding structure, and circuit depth in stabilizer measurement.