Hierarchical Logical Processor on the Rotated Surface Code with Shuttle Buses

Abstract: Quantum platforms with beyond-planar connectivity provide new opportunities for fault-tolerant quantum computation (FTQC). While quantum low-density parity-check (qLDPC) codes offer high encoding efficiency, their direct implementation requires non-local couplings in every round of syndrome extraction, incurring additional physical error and implementation complexity. To reduce the frequency of such couplings, we propose the Hierarchical Logical Processor (HLP), which concatenates a high-rate quantum CSS code with the rotated surface code (RSC). HLPs can achieve beyond-RSC encoding efficiency while requiring long-range connectivity only once every $Θ(d_0)$ rounds of level-0 error correction, where $d_0$ denotes the base-code distance, substantially reducing the frequency of non-local couplings relative to direct implementations of qLDPC codes. HLPs introduce elongated RSC patches called shuttle buses. Using transversal hybrid-unit CNOT gates, a single shuttle bus can simultaneously couple to multiple standard RSC patches. This capability enables efficient level-1 syndrome extraction with suppressed level-1 error correlations and supports highly parallel logical Pauli measurements. We perform circuit-level simulations of several concrete HLP constructions and benchmark both logical memory and logical Pauli measurement performance. At a physical error rate of $10^{-3}$, an HLP based on the [[256,194,4]] code achieves 3-4 times higher qubit efficiency than the standard RSC. Compared with the yoked surface code on the same level-1 code, this HLP reduces the space overhead per logical qubit by 100-200 physical qubits and shortens the logical error-correction cycle time by a factor of 20-30.

• The paper presents the Hierarchical Logical Processor (HLP) framework that concatenates high-rate CSS codes with the rotated surface code to boost encoding efficiency while minimizing long-range gate usage.
• It employs shuttle bus structures and hybrid-unit transversal CNOT gates to enable parallel syndrome extraction and controlled error propagation under depolarizing noise.
• Simulations indicate that the HLP reduces space overhead by up to 200 qubits and accelerates logical measurements by a factor of 20–30, highlighting its potential for scalable fault-tolerant quantum computation.

Hierarchical Logical Processor on the Rotated Surface Code with Shuttle Buses

Introduction and Motivation

Fault-tolerant quantum computation (FTQC) necessitates quantum error correction codes (QECCs) that minimize logical error rates with practical resource overhead. The rotated surface code (RSC) is a dominant candidate due to high threshold and practicality, but its qubit efficiency is limited—all distance-$d$ RSCs encode a single logical qubit in $d^2$ physical qubits. In contrast, recent quantum low-density parity-check (qLDPC) code constructions offer improved encoding rates, but generically require non-planar, non-local connectivity per syndrome extraction (SE) round, presenting considerable hardware and error propagation challenges, especially in platforms with reconfigurable, but noise-prone, long-range couplings.

This paper introduces the Hierarchical Logical Processor (HLP): a concatenated code architecture that achieves high encoding efficiency while mitigating the frequency of long-range gates by leveraging shuttle bus structures. HLP concatenates a high-rate CSS code (as a level-1 code) with the RSC (level-0 code), using elongated RSC patches ("shuttle buses") for efficient, parallelizable, and minimally correlated syndrome extraction and logical measurement.

HLP Architecture

The HLP's basic units consist of cores (standard RSC patches of distance $d_0$) acting as level-1 data qubits, and shuttle buses (elongated RSCs of width $d_0$, length $d_0 d_1$) providing level-1 ancilla qubits (Fig. 1). The shuttle bus design accommodates bus-core and core-bus hybrid-unit transversal CNOT gates, which couple a bus simultaneously to up to $d_1$ cores, or vice versa. This enables syndrome extraction and logical measurement with a spatial and temporal separation that suppresses error correlations, allowing long-range interactions only once every $\Theta(d_0)$ level-0 SE rounds per working unit.

Figure 1: Architecture of a hierarchical logical processor. (a) Basic working units: cores and shuttle buses. (b,c) Hybrid-unit CNOT gates: bus-core and core-bus. (d,e) Level-1 $X$ and $Z$ readout gadgets implemented by boxed hybrid CNOTs and time padding.

Hybrid-unit CNOT gate sparsity is quantified with two compilation parameters: $\alpha_{\mathsf{b}}$ (CNOT separation on shuttle buses) and $d^2$0 (CNOT separation on cores). Theoretical analysis (supported by rigorous error propagation/leakage bounds) establishes that $d^2$1 and $d^2$2 suffice to suppress error correlations under a phenomenological depolarizing noise model. This architecture minimizes the temporal overhead for logical operations without compromising error locality.

Syndrome Extraction and Logical Measurement

Each level-1 stabilizer (from the high-rate CSS code) is extracted via a readout gadget, which uses a shuttle bus as ancilla (in $d^2$3 or $d^2$4 basis), interacting transversally with associated cores. The buses are initialized and measured transversally; between hybrid unit CNOT operations, sufficient level-0 SE rounds are imposed to suppress error propagation.

Parallelization is a core capability: multiple logical Pauli operators can be measured simultaneously by packing their readout gadgets densely, as bus-qubit interactions commute when acting on disjoint supports. Importantly, such packing does not appreciably increase the logical error rate, as confirmed by numerical simulations.

Figure 2: Benchmarking of HLPs. (a) Level-1 layout of a Square Berg code HLP. (b) Logical error rates vs. core distance for several HLP codes and RSC. (c,d) Qubit and time overhead vs. logical error rate for several codes.

Logical measurement of general Pauli observables (including non-$d^2$5) is achieved by sequences of standard, $d^2$6-transformed, or $d^2$7-transformed readout gadgets, utilizing transversal $d^2$8 or $d^2$9 gates embedded in the shuttle bus. The need for mid-cycle logical Clifford gates can be fulfilled by fold-transversal implementations compatible with the bus architecture, e.g., mid-cycle $d_0$0 as shown in the supplementary figures.

Decoding and Error Model

The decoding pipeline is hierarchical:

1. Level-0 (RSC) detectors and errors are modeled, taking into account the effect of hybrid-unit gates and syndrome extraction boundaries.
2. Residual level-0 errors after matching-based decoding are projected to primitive level-1 errors via a rigorous combinatorial framework (tracking cycles, walks, and error propagation through CNOT membranes).
3. Level-1 (high-rate code) decoding is performed using soft-output probabilities derived from level-0 decoding.

Theoretical guarantees demonstrate that, provided rare high-weight cycles are absent (with probability exponentially suppressed in $d_0$1), induced level-1 $d_0$2/$d_0$3 errors are local stochastic, with effective rate $d_0$4 if physical error rate is $d_0$5. In practical hardware regimes, this yields logical error rates scaling exponentially in the total HLP code distance $d_0$6.

Numerical Results and Comparative Performance

Comprehensive circuit-level simulations corroborate the theoretical bounds. For physical error rate $d_0$7:

• A HLP constructed from the Square Berg code achieves 3–4× higher qubit efficiency than RSC, and reduces space overhead per logical qubit by 100–200 qubits relative to the yoked surface code, at equivalent target logical error rates (from $d_0$8 to $d_0$9).
• Level-1 syndrome extraction round time is reduced by a factor of 20–30.
• Level-1 logical error rate decays with distance at nearly twice the rate of RSC.

  Figure 3: Logical Pauli measurements on a HLP. (a) Z-basis logical measurement sequence. (b) Densely packed measurement gadgets. (c) Performance comparison: logical error rates for memory, measurement, and parallel measurement circuits.

Parallel logical measurements via the LMS protocol (sequences of readout gadgets) yield performance only marginally worse than sequential memory operation, demonstrating strong parallelizability and negligible excess correlated failure probability. Theoretical bounds on logical measurement errors scale as $d_0$0, but simulation indicates nearly optimal $d_0$1 scaling is achievable in realistic conditions due to soft-output informed level-1 decoding.

Extensions and Interfacing

The architecture supports flexible interfacing with external RSC patches (cores of arbitrary distance $d_0$2), permitting HLP-external joint Pauli measurements with error rates scaling as $d_0$3. Hence, heterogeneous hybrid architectures composed of HLPs and individual code patches can be scheduled to collaboratively implement logical Clifford circuits, state preparation, and joint measurements.

Implementation Prospects and Outlook

Neutral atom arrays with dynamic long-range connectivity are a promising hardware substrate, with native bus and core implementations possible via static and shuttled zones, or all-in-place schemes. The HLP's demand for infrequent long-range gates matches well with architectures where such operations are slower or more error-prone. Theoretical and empirical analysis suggests the possibility of further resource reduction by replacing the RSC base code with small qLDPCs or using higher-rate level-1 codes.

Future directions include:

• Optimization of bus scheduling, gadget parallelization, and error decoding for faster operation.
• Hybridization with additional logical gate paradigms (such as transversal/fold-transversal non-Clifford gates).
• Extension to architectures with repeated measurement or where hardware efficiency varies dramatically between local and long-range gates.

Conclusion

HLPs extend the RSC paradigm by combining high encoding efficiency, low overhead, and strong practical parallelism for logical operations, with infrequent demand for non-local couplings and rigorous control of error propagation and correlation. Both theoretical and simulation results demonstrate substantial improvements in resource efficiency over standard RSC and yoked surface code architectures, providing a scalable and pragmatic pathway toward fault-tolerant quantum computation in platforms with (moderately) reconfigurable connectivity.