Exact Multiple-input Binary Accumulator (EMBA)

• EMBA is a deterministic multi-input bitstream adder that performs exact binary accumulation using integer addition over temporal encoded pulses.
• Architectural realizations include counter-based, serialized, and exponent-indexed designs that replace approximate scaled adders with precise operations.
• Integration of EMBA into MAC units improves accuracy, power efficiency, and area utilization in applications such as FIR filters and DCT engines.

Searching arXiv for the cited papers and closely related accumulator work to ground the article. Exact Multiple-input Binary Accumulator (EMBA) denotes, in the terminology of Enhanced Hybrid Temporal Computing, a bitstream adder that performs precise binary accumulation over multiple-input bitstreams and replaces the approximate MUX-based scaled adder used in earlier Hybrid Temporal Computing MACs (Sachdeva et al., 26 Sep 2025). In the visible EMBA literature, the term is explicit in temporal computing, whereas adjacent work describes structurally related exact accumulators without using the same label: accumulator-aware post-training quantization constrains integer dot-product sums to avoid overflow in narrow accumulators (Colbert et al., 2024), Bit Layer Multiplier Accumulator (BLMAC) realizes exact fixed-point dot products using additions, subtractions, and shifts (Liguori, 2024), and exponent-indexed accumulators sum mantissas exactly across exponent buckets before reconstruction (Liguori, 2024). This suggests EMBA is best treated as a family resemblance across exact temporal, integer, and floating-point accumulation mechanisms rather than as a single canonical circuit template.

1. Definition and formal meaning

In the E-HTC formulation, EMBA is a deterministic multi-input temporal bitstream adder. Its defining property is exactness with respect to the encoded bitstreams: given binary streams $x_i(t) \in \{0,1\}$, it forms the per-cycle pulse count

$p(t) = \sum_{i=1}^{N} x_i(t),$

and the accumulated result after $T$ cycles is

$$S(T) = \sum_{t=1}^{T} p(t) = \sum_{t=1}^{T} \sum_{i=1}^{N} x_i(t).$$

For unipolar encoding,

$$X_i^{(\text{unipolar})} = \frac{1}{T} \sum_{t=1}^{T} x_i(t),$$

so EMBA computes the exact sum of the encoded values after normalization by $T$. For bipolar encoding,

$$X_i^{(\text{bipolar})} = \frac{1}{T} \sum_{t=1}^{T} \big(2x_i(t)-1\big),$$

and

$$\sum_{i=1}^{N} X_i^{(\text{bipolar})} = \frac{2S(T)-NT}{T}.$$

Under this description, EMBA is exact because it performs integer addition at every step rather than probabilistic selection or scaled averaging (Sachdeva et al., 26 Sep 2025).

A related exactness notion appears in exponent-indexed accumulation. If inputs are written as $x_i = m_i 2^{e_i}$, then accumulation proceeds by grouping mantissas by exponent,

$$S[e] = \sum_{i:e_i=e} m_i, \qquad \sum_{i=0}^{N-1} m_i 2^{e_i} = \sum_e S[e]2^e,$$

with normalization deferred until reconstruction. The cited formulation states that all bits shifted out during reconstruction, together with the final value of the reconstruction accumulator, represent the exact result of the sum of all the input numbers. Numerically, this is the same exact-accumulation objective pursued by EMBA, although in a different architecture (Liguori, 2024).

2. Architectural realizations

The E-HTC EMBA is described as a multiple-input counter-based accumulator. Architecturally, it consists of a multi-input binary adder or adder tree that counts the number of $p(t) = \sum_{i=1}^{N} x_i(t),$0s present at a cycle and a running accumulator that adds this count to a stored sum. In that setting, EMBA is the exact accumulation stage inside a MAC unit that supports both unipolar and bipolar encodings. Its role is specifically to replace the MUX-based scaled addition used in the original HTC architecture, thereby removing scaling and random-selection error from accumulation (Sachdeva et al., 26 Sep 2025).

BLMAC shows that exact multiple-input accumulation need not be spatially parallel. There, weights are decomposed into bit layers,

$p(t) = \sum_{i=1}^{N} x_i(t),$1

so the dot product becomes

$p(t) = \sum_{i=1}^{N} x_i(t),$2

The architecture is “an add/sub accumulator plus a 2:1 multiplexer to select the shift operation.” Each non-zero digit is a pulse that triggers addition or subtraction of an input sample, and shifts implement the powers of two associated with bit layers. Conceptually, each layer is a multiple-input sum, but the hardware serializes those inputs over time. The result remains exact because the computation uses full fixed-point addition, subtraction, and single-bit shifts, with no truncation in the middle of the computation (Liguori, 2024).

Exponent-indexed accumulators provide a third realization. Mantissas are accumulated into per-exponent buckets during an accumulation phase, and a reconstruction phase then emits the exact result in a bit-serial or grouped fashion. The grouping parameter $p(t) = \sum_{i=1}^{N} x_i(t),$3 interpolates between one bucket per exponent at $p(t) = \sum_{i=1}^{N} x_i(t),$4 and a Kulisch accumulator at $p(t) = \sum_{i=1}^{N} x_i(t),$5. The cited discussion states explicitly that for $p(t) = \sum_{i=1}^{N} x_i(t),$6 the method becomes the Kulisch accumulator, so the architecture family spans distributed and monolithic exact accumulators within one parameterization (Liguori, 2024).

3. Exactness, range, and overflow

Exact accumulation is conditional on representable range. In accumulator-aware quantization, the hardware-visible integer sum for one quantized dot product is

$p(t) = \sum_{i=1}^{N} x_i(t),$7

and overflow occurs when

$p(t) = \sum_{i=1}^{N} x_i(t),$8

for a signed accumulator of width $p(t) = \sum_{i=1}^{N} x_i(t),$9. The cited analysis emphasizes that low-bit multipliers can make multiplication cheap while additions still dominate power and area in the MAC unit, and that reducing accumulator precision can improve throughput and energy efficiency but drastically raises overflow risk. This makes accumulator sizing a first-order design parameter rather than a secondary implementation detail (Colbert et al., 2024).

The same work gives explicit sufficient conditions for overflow avoidance. For unsigned $T$0-bit activations and zero-sum quantized weights,

$T$1

which directly bounds dot-product dynamic range. For binary activations $T$2 and binary weights $T$3, the worst-case sum is $T$4, so exact accumulation requires

$T$5

That condition is the simplest EMBA sizing rule: a multiple-input binary accumulator must be able to represent the maximum count of active inputs. The same source extends the analysis to multi-stage accumulation and gives

$T$6

where $T$7 is the inner-accumulator width, $T$8 the outer-accumulator width, $T$9 the dot-product depth, and $$S(T) = \sum_{t=1}^{T} p(t) = \sum_{t=1}^{T} \sum_{i=1}^{N} x_i(t).$$0 the tile size. This is directly applicable to tree-based or tiled EMBA datapaths (Colbert et al., 2024).

BLMAC frames the same issue in fixed-point FIR arithmetic. Its exactness depends on choosing accumulator width adequately and applying truncation or rounding only at the end. The right-shift variant has the special property that, at the end of processing bit layer $$S(T) = \sum_{t=1}^{T} p(t) = \sum_{t=1}^{T} \sum_{i=1}^{N} x_i(t).$$1, the least significant bit shifted out is exactly the $$S(T) = \sum_{t=1}^{T} p(t) = \sum_{t=1}^{T} \sum_{i=1}^{N} x_i(t).$$2-th bit of the final result and can be safely recorded or discarded. In other words, exactness is preserved so long as internal range and carry propagation are sufficient (Liguori, 2024).

4. Integration into MACs and signal-processing pipelines

Within E-HTC, EMBA is integrated into the multiplier-accumulator unit as the accumulation stage that sums outputs of temporal multipliers. The MAC supports unipolar and bipolar encodings, and the same MAC template is then used in a Finite Impulse Response filter and an 8-point Discrete Cosine Transform/iDCT engine. In that pipeline, EMBA is the deterministic accumulation backbone, while the companion Deterministic Threshold-based Scaled Adder (DTSA) serves as a deterministic but approximate alternative (Sachdeva et al., 26 Sep 2025).

BLMAC demonstrates a closely related integration strategy in FIR filtering. For type I symmetric FIR filters, symmetry reduces the effective dot product by pre-adding symmetric samples, after which the accumulator processes the resulting effective inputs layer by layer. The described datapath includes sample memory, a pre-adder, weight memory storing run-length encoded ternary pulses, a run-length expander, the BLMAC accumulator, and a shift register in the right-shift version. This is a serial multiple-input binary accumulation pipeline over time, driven by bit-layer sparsity rather than by direct multiplication (Liguori, 2024).

Accumulator-aware post-training quantization offers a co-design path for narrow exact accumulators in neural inference. AXE augments layer-wise PTQ algorithms such as GPFQ and OPTQ with a soft global $$S(T) = \sum_{t=1}^{T} p(t) = \sum_{t=1}^{T} \sum_{i=1}^{N} x_i(t).$$3-norm regularization and a strict local clipping rule so that partial sums of positive and negative weights remain within accumulator-safe budgets. The framework is generalized to multi-stage accumulation, allowing inner accumulators inside atomic MAC units and an outer accumulator for partial sums. Although the term EMBA is not used explicitly there, the framework provides the theoretical constraints needed to ensure that a narrow accumulator behaves exactly because overflow is made provably absent (Colbert et al., 2024).

Exponent-indexed accumulation extends the same integration logic to floating-point, posit, and logarithmic MACs. The architecture fuses multiplication with accumulation by multiplying mantissas, adding exponents, and then sending the resulting mantissa to an exponent-indexed partial-sum structure. Reconstruction is separate from accumulation, which allows exact summation without immediate normalization. This suggests a generalized EMBA viewpoint in which exactness is maintained even when inputs are not ordinary temporal bitstreams but encoded floating-point-like values (Liguori, 2024).

5. Empirical behavior and reported trade-offs

The clearest EMBA-specific empirical data comes from E-HTC. On a 4x4 MAC in unipolar mode, E-HTC matches the RMSE of state-of-the-art Counter-Based Stochastic Computing MAC, improves accuracy by 94% over MUX-based HTC, and reduces power and area by 23% and 7% compared to MUX-based HTC and 64% and 74% compared to CBSC. In bipolar mode, E-HTC MAC achieves $$S(T) = \sum_{t=1}^{T} p(t) = \sum_{t=1}^{T} \sum_{i=1}^{N} x_i(t).$$4 RMSE, an 83% improvement over MUX-based HTC, and approaches CBSC’s $$S(T) = \sum_{t=1}^{T} p(t) = \sum_{t=1}^{T} \sum_{i=1}^{N} x_i(t).$$5 RMSE with area and power savings of 28% and 43% versus MUX-based HTC and about 76% versus CBSC. In FIR experiments, both E-HTC variants yield PSNR gains of $$S(T) = \sum_{t=1}^{T} p(t) = \sum_{t=1}^{T} \sum_{i=1}^{N} x_i(t).$$6–$$S(T) = \sum_{t=1}^{T} p(t) = \sum_{t=1}^{T} \sum_{i=1}^{N} x_i(t).$$7 dB, corresponding to $$S(T) = \sum_{t=1}^{T} p(t) = \sum_{t=1}^{T} \sum_{i=1}^{N} x_i(t).$$8–$$S(T) = \sum_{t=1}^{T} p(t) = \sum_{t=1}^{T} \sum_{i=1}^{N} x_i(t).$$9 RMSE reduction, while saving 13% power and 3% area. For DCT/iDCT, E-HTC boosts PSNR by $$X_i^{(\text{unipolar})} = \frac{1}{T} \sum_{t=1}^{T} x_i(t),$$0–$$X_i^{(\text{unipolar})} = \frac{1}{T} \sum_{t=1}^{T} x_i(t),$$1 dB, corresponding to $$X_i^{(\text{unipolar})} = \frac{1}{T} \sum_{t=1}^{T} x_i(t),$$2–$$X_i^{(\text{unipolar})} = \frac{1}{T} \sum_{t=1}^{T} x_i(t),$$3 RMSE reduction, while saving area and power over both MUX- and CBSC-based designs (Sachdeva et al., 26 Sep 2025).

BLMAC reports complementary evidence from fixed-point FIR workloads. A total of 1,980,000 low, high, band pass and band stop type I FIR filters were generated by systematically sweeping through the cut off frequencies and by varying the number of taps from 55 to 255. After coefficients were quantized to 16 bits, applying the filter using a BLMAC required, on average, from approximately 123.3 to 513.6 additions, depending on the number of taps. A BLMAC dot product machine specialized for 127 taps FIR filters was designed for AMD FPGAs; the design footprint is approximately 110 LUTs, including coefficient and sample storage, and the filter is applied in approximately 232 clock cycles on average, implying 1.4–3.4 Msamples/s depending on the FPGA family (Liguori, 2024).

In quantized neural inference, AXE reports Pareto frontiers over accumulator width and accuracy. For ResNet-18, MobileNetV2, and ViT-B-32 on ImageNet, AXE allows reducing $$X_i^{(\text{unipolar})} = \frac{1}{T} \sum_{t=1}^{T} x_i(t),$$4 down to approximately 14–16 bits with modest accuracy loss, significantly better than naive bit-width manipulation or EP-init. For LLMs including OPT-125M, GPT2-137M, and Pythia-160M on WikiText2, AXE substantially reduces the accuracy gap at low accumulator widths compared to baseline methods. For larger Pythia models with multi-stage accumulation, the constrained models’ perplexity approaches unconstrained quantized models for fixed inner accumulator width, which the source describes as supporting a scaling hypothesis (Colbert et al., 2024).

For floating-point-like exact accumulation, exponent-indexed architectures report hardware evidence rather than application-level error metrics. The cited tensor core multiplies and accumulates two 4x4 matrices of bfloat16 values every clock cycle using approximately 6,400 LUTs plus 64 DSP48 in AMD FPGAs at 700+ MHz. The same work also gives example FPGA figures for a single bfloat16 MAC and extends the design to posits and logarithmic numbers, framing exact accumulation as a practical hardware option rather than merely a numerical idealization (Liguori, 2024).

6. Relation to neighboring concepts and common misunderstandings

A common misunderstanding is to equate EMBA with a particular adder tree. The literature does not support that restriction. The E-HTC version is naturally described as a multi-input counter-based accumulator, but BLMAC shows that multiple-input binary accumulation can be serialized over time, and exponent-indexed accumulation shows that exactness can also be achieved by distributing partial sums across exponent-indexed buckets and reconstructing later. “Multiple-input” therefore refers to the arithmetic role rather than to a mandatory parallel topology (Sachdeva et al., 26 Sep 2025).

A second misunderstanding is that exact accumulation automatically implies a single very wide accumulator. Exponent-indexed accumulators explicitly contradict that assumption: for $$X_i^{(\text{unipolar})} = \frac{1}{T} \sum_{t=1}^{T} x_i(t),$$5 there is one partial sum register per exponent, while for $$X_i^{(\text{unipolar})} = \frac{1}{T} \sum_{t=1}^{T} x_i(t),$$6 the method becomes the Kulisch accumulator. The exact same numerical objective can thus be realized by bucketized accumulation, grouped accumulation, or a monolithic fixed-point accumulator, with $$X_i^{(\text{unipolar})} = \frac{1}{T} \sum_{t=1}^{T} x_i(t),$$7 controlling the trade-off (Liguori, 2024).

A third misunderstanding is that accumulator exactness makes quantization constraints irrelevant. AXE reaches the opposite conclusion. Low-precision accumulation may improve throughput, power, and area, but correctness depends on keeping the sum inside the available range. The framework therefore constrains weights, activations, and scales so that overflow is provably absent. This is particularly important for binary and very low-precision datapaths, where the arithmetic is simple but the margin to overflow is narrow (Colbert et al., 2024).

Finally, exact accumulation should not be conflated with exact end-to-end computation. In E-HTC, EMBA is exact for the encoded accumulation step, yet the reported systems still evaluate RMSE and PSNR because overall accuracy also depends on temporal encoding, multiplier behavior, finite bitstream length, and quantization. The contrast with DTSA makes the point clearer: DTSA is deterministic but approximate, whereas EMBA is the exact reference accumulator inside the same framework (Sachdeva et al., 26 Sep 2025).