Exact Posit Accumulation

• Exact Posit Accumulation is a method for summing posit numbers exactly by aggregating significands in a common fixed-point format, eliminating intermediate rounding errors.
• It employs techniques like exponent-indexed accumulation and the quire accumulator to ensure high precision in dot-products and long reductions.
• This methodology enhances numerical kernels in scientific computing and DNN accelerators by significantly reducing error and improving robustness.

Exact Posit Accumulation is a methodology for summing, or multiplying and accumulating, sequences of numbers represented in the posit number format such that the result is bitwise-exact up to a final rounding, avoiding the intermediate rounding errors typical in floating-point or naively implemented posit arithmetic. The main paradigm uses either multi-bucket, exponent-indexed accumulators or a wide fixed-point register known as the quire. These approaches enable the exact capture of large sums or dot-products, allowing for much higher numerical accuracy, associative reduction, and robustness in both hardware and software implementations. Their adoption has resulted in significant improvements in numerical kernels and has driven architectural innovation in both domain-specific accelerators and general-purpose processors supporting posit arithmetic (Liguori, 2024, Mallasén et al., 2021, Mallasén et al., 2023, Carmichael et al., 2018, Sharma et al., 2020).

1. Theoretical Foundations

Posit exact accumulation leverages key structural aspects of the posit format. Each n-bit posit encodes a number via variable-length regime, exponent, and fraction fields, such that

$p = (-1)^s \cdot \useed^k \cdot 2^e \cdot (1.f)$

where $s$ is the sign, $k$ is obtained from the regime field through run-length decoding, $e$ the (possibly batched) exponent, and $f$ the implicit fraction (Carmichael et al., 2018, Mallasén et al., 2023). In dot-products or long accumulations, direct addition or FMA typically leads to repeated rounding and loss of associativity, especially as dynamic range and operand count increase.

Exact posit accumulation recasts the sum so that all significand additions are performed in a common, wide fixed-point representation—a direct analogy to a Kulisch accumulator in floating-point arithmetic. For N terms $p_i$, this process is mathematically formalized as

$$\sum_{i=0}^{N-1} (-1)^{s_i} (1.f_i) 2^{E_i} = \sum_E \left(\sum_{\substack{i: E_i = E}} m_i\right) 2^E$$

where $m_i$ are integer-valued mantissas and $E_i$ are the effective exponents (regime plus exponent bias) (Liguori, 2024).

2. Algorithms and Data Structures

a. Exponent-Indexed Accumulation

The two-phase exponent-bucket method is described for posits as follows (Liguori, 2024):

• Phase 1: Each input posit $p_i$ is decoded into sign, regime, exponent, and fraction. The integer mantissa $s$0 is formed and stored in an array $s$1 indexed by $s$2:

$s$3

No rounding occurs since all bucket additions are on fixed-width integers.

• Phase 2: The range of occupied buckets $s$4 is traversed bitwise, performing a shift-and-add reconstruction

$s$5

yielding the final bit-accurate sum.

b. Quire Accumulator

The quire is a wide 2’s-complement fixed-point register, with bit-width calculated as (Posit Standard)

$s$6

or, in hardware practice, sometimes $s$7 or $s$8 (Mallasén et al., 2021, Mallasén et al., 2023, Sharma et al., 2020).

• Each product (in dot-product or MAC) is aligned and exactly added to the quire.
• After all terms, a single normalization and rounding operation maps the quire back to an $s$9-bit posit.
• No intermediate rounding is performed, ensuring exactness.

c. Resource and Bitwidth Analysis

Key parameters:

• Exponent bucket method: For $k$0 regime and $k$1 exponent bits, $k$2 accumulator buckets are needed, each wide enough for the maximum mantissa sum plus $k$3 bits (Liguori, 2024).
• Quire method: Bitwidths range from 32 (n=8) up to 1024 (n=64), dominating hardware requirements; the center of the register aligns with zero, supporting wide shifts for high dynamic range (Carmichael et al., 2018, Sharma et al., 2020).

3. Hardware and Architecture Implementations

A variety of architectures for exact posit accumulation have been described:

• FPGA/ASIC realization of exponent-indexed accumulators (ex: tensor MACs and neural network cores): All variable-length decoders (regime/exponent/fraction extraction) precede high-throughput RAM and adder arrays, with cycle-accurate pipelining supporting 1 posit/cycle throughput and up to 1 output-bit/cycle in reconstruction (Liguori, 2024, Carmichael et al., 2018).
• Quire in general-purpose RISC-V cores: In PERCIVAL (32/64b posit + quire), a 512/1024-bit quire register resides in the posit arithmetic unit (PAU), supporting hardware ISAs for fused multiply-accumulate (QMADD, QMSUB) and final conversion (QROUND) (Mallasén et al., 2021, Mallasén et al., 2023, Sharma et al., 2020).
• Specialized pipeline extensions: Clarinet’s Melodica core, with three-stage posit extraction/multiply/accumulate, demonstrates pipeline-level sharing between floating-point and posit domains, with resource utilization heavily weighted toward the quire register (Sharma et al., 2020).
• Precision-tunable soft cores: FPGA-based DNN accelerators parameterize posit EMAC units by n and es, balancing LUT/FF use with delay and accuracy (Carmichael et al., 2018).

Hardware Resource Table

System	Quire Width (bits)	Extra LUTs with Quire	Throughput
PERCIVAL-32	512	+11,879	1 accum/cycle
PERCIVAL-64	1024	+13,822	1 accum/cycle
Melodica	32/128/512	1.5K/3.2K/9.6K	pipelined
FPGA Posit EMAC	32–1024	20–30% > float EMAC	~200–250 MHz

4. Accuracy, Performance, and Trade-offs

Exact posit accumulation achieves dramatic improvements in accumulated sum accuracy, with error reductions of up to four orders of magnitude over IEEE-754 single or double-precision arithmetic in dot-products and GEMM (Mallasén et al., 2021, Mallasén et al., 2023, Sharma et al., 2020). For example:

• On GEMM with 32-bit posits and quire, mean squared error can decrease from $k$4 (float) to $k$5 (posit+quire) (Mallasén et al., 2021).
• Scientific workloads (e.g., conjugate gradient solvers) converge in 2.5–19% fewer iterations with posit64+quire vs double (Mallasén et al., 2023).
• In resource-limited scenarios (e.g., DNN inference with $k$6), posit EMAC with exact quire accumulation preserves accuracy within 1–2% of 32-bit float, outperforming 8-bit float/fixed-point by 1–3% (Carmichael et al., 2018).

Performance is contingent on memory bandwidth and pipeline utilization. For high fan-in or BLAS-1 kernels (long reductions):

• Quire-based posit runs as fast as, or even faster than, float32 with FMADD, due to pipelined accumulation stages (Mallasén et al., 2021, Sharma et al., 2020).
• The hardware area and energy costs are substantial; a posit+quire FPU can require up to 2–5× the logic area and power of a standard IEEE FPU (Mallasén et al., 2023, Sharma et al., 2020).

A single quire register per core restricts concurrency for overlapping dot-products, so software must sequence reductions to avoid spillage and may incur conversion overhead when switching between posit and float (Mallasén et al., 2021, Sharma et al., 2020).

5. Applications and Impact

Exact posit accumulation is most effective in domains dominated by long reductions, dot products, or matrix multiplications:

• Scientific computing: In large linear algebra workloads, Big-PERCIVAL demonstrates up to four orders of magnitude lower mean squared error than IEEE double, unlocking higher accuracy or allowing reduced n for bandwidth-limited problems (Mallasén et al., 2023).
• Deep neural networks: FPGA DNN architectures using posit EMAC enable working with 8-bit or even 7-bit weights/activations without major degradation in inferential accuracy, reducing memory and computational cost by factors of 4–8 (Carmichael et al., 2018).
• Computer vision: Optical flow kernels see an order-of-magnitude error reduction when using quire-based p32-q32 accumulations compared to f32 (Sharma et al., 2020).
• General-purpose processors: Native RISC-V ISA support (XPosit, Melodica extension) positions posits and their quire as viable alternatives to float, supporting rapid switching and cross-comparison in hardware (Mallasén et al., 2021, Sharma et al., 2020).

6. Limitations, Parameterization, and Design Considerations

The main limitation of exact posit accumulation is the hardware resource cost. The quire size grows rapidly with n and moderately with exponent size es:

• For $k$7: $k$8; for $k$9: $e$0 (Mallasén et al., 2021, Mallasén et al., 2023, Sharma et al., 2020).
• Large quires dominate area and power; e.g., a 64-bit posit w/ quire core is $e$1 area/power of a double-precision FPU (Mallasén et al., 2023).
• The exponent-bucket method requires memory proportional to the number of distinct exponent values, mitigated by storing only within the observed exponent window (Liguori, 2024).
• Accumulating few terms per sum or performing many short reductions causes underutilization and increases relative latency, especially with large quires (Sharma et al., 2020).
• There is no loss in round-off beyond the final rounding stage; however, catastrophic cancellation at the sum level is not mitigated by exact accumulation.

Parameter selection for n and es is application dependent. Lower n and small es provide high precision and efficient hardware for embedded/tinyML; higher n and es support large scientific workloads but incur much higher cost (Carmichael et al., 2018, Sharma et al., 2020).

7. Outlook and Research Directions

Ongoing research aims to:

• Integrate exact posit accumulation into mainstream toolchains and libraries, continuing work on RISC-V and LLVM extensions (Mallasén et al., 2021, Sharma et al., 2020).
• Optimize and compress quire hardware, e.g., segmenting, zero-flag optimizations, and dynamic scaling (Sharma et al., 2020).
• Develop algorithms to dynamically select accumulation modes based on sum depth and dynamic range (Carmichael et al., 2018, Liguori, 2024).
• Explore mixed-precision and adaptive posit sizing for further bandwidth and energy gains (Mallasén et al., 2023).

A plausible implication is that widespread adoption of posit+quire architectures will enable the re-examination of numerical kernel design, reducing reliance on ad hoc scaling/ordering tricks to manage floating-point round-off and unlocking new classes of hardware-robust, error-resilient scientific computation.